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authorTim Harvey <tharvey@gateworks.com>2025-07-07 13:16:58 -0700
committerShawn Guo <shawnguo@kernel.org>2025-07-11 16:34:33 +0800
commitbd49cb58b59f1c2e27495f347a460f45be71200d (patch)
treee88c44d6f267e9c75a479669f94770a2a8e1f1b1 /scripts/gdb/linux/proc.py
parent81b07d51cda761eecc36bed907a1c88d2adeb689 (diff)
arm64: dts: imx8mm-venice-gw7901: Increase HS400 USDHC clock speed
The IMX8M reference manuals indicate in the USDHC Clock generator section that the clock rate for DDR is 1/2 the input clock therefore HS400 rates clocked at 200Mhz require a 400Mhz SDHC clock. This showed about a 1.5x improvement in read performance for the eMMC's used on the various imx8m{m,n,p}-venice boards. Fixes: 2b1649a83afc ("arm64: dts: imx: Add i.mx8mm Gateworks gw7901 dts support") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Link: https://lore.kernel.org/stable/20250707201702.2930066-3-tharvey%40gateworks.com Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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