diff options
| author | Marijn Suijten <marijn.suijten@somainline.org> | 2022-10-30 08:32:23 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-11-07 17:25:46 -0600 |
| commit | e10d451e10418f12e72ed8564f22fdba8b10a9b0 (patch) | |
| tree | e8a93330580e366f36cc29e6bc113063a99d1fe0 | |
| parent | ce1b5eb74b3ef042b1c797f04e8683e7cad34ae6 (diff) | |
arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2
Make sure the SDHCI hardware is properly reset before interacting with
it, to protect against any possibly indeterminate state left by the
bootloader.
Suggested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030073232.22726-2-marijn.suijten@somainline.org
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 3a315280c34a..2806194e6959 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -490,6 +490,7 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd SM6350_CX>; @@ -1068,6 +1069,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; |