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| author | Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> | 2025-07-22 05:50:39 +0000 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-08-11 16:43:43 -0500 |
| commit | bebacd802b51fae87e04a0f2b6eeb66ac259c14e (patch) | |
| tree | 6d4819cc3c3afb3dfa21535d579e4525cb56ef86 /scripts/gdb/linux/radixtree.py | |
| parent | df758a868dbc90cae98044d52a9d753575f50cfa (diff) | |
arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP OPP tables to scale DDR/L3
Add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables
required to scale DDR and L3 per freq-domain on QCS8300 platform.
As QCS8300 and SA8775P SoCs have same EPSS hardware, added SA8775P
compatible as fallback for QCS8300 EPSS device node.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722055039.135140-2-raviteja.laggyshetty@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/radixtree.py')
0 files changed, 0 insertions, 0 deletions