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authorQiang Yu <qiang.yu@oss.qualcomm.com>2025-07-22 17:11:50 +0800
committerBjorn Andersson <andersson@kernel.org>2025-08-11 16:43:07 -0500
commit6facfaff0fe3b4d5903bed6164eb5e60ee6cdb8f (patch)
treed351e5638482b614ed0f686ddd23bc188d7134ab /scripts/gdb/linux/xarray.py
parentf93e5882134a314760d47536d93b57fbd32d0da1 (diff)
arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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