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authorRavi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>2025-11-05 11:07:06 -0300
committerGustavo Sousa <gustavo.sousa@intel.com>2025-11-06 18:23:27 -0300
commitdeb769920ebf905580d24b3ad18a9f804b72147a (patch)
tree7199964b4815cac7312149643d652d64ea5eba4b /tools/lib/python/kdoc/python_version.py
parente2a06cf825ef07f3c657b9434abe5269aff8a56b (diff)
drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to accommodate for higher MDCLK:CDCLK ratios. Update the code to use the new fields. The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range [15:13] to [16:13]. Since bit 16 is not reserved in previous display IPs and already used for something else, we can't simply extend the mask definition to include it, but rather define an Xe3p-specific mask and select the correct one to use based on the IP version. Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range [18:16] to [20:16]. For the same reasons stated above, it needs a Xe3p-specific mask definition. v2: - Keep definitions in the same line (i.e. without line continuation breaks) for better readability. (Jani) v3: - Keep mask fields sorted by the upper limit. (Matt) - Extend commit message to indicate why we need Xe3p-specific definitions of the masks instead of just extending the existing ones. (Matt) Bspec: 68868, 68872 Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-18-00e87b510ae7@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
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