drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency

When reading memory latencies for watermark calculations, previous
display releases instructed to apply an adjustment of adding a certain
value (e.g. 6us) to all levels when the level 0's memory latency read
from hardware was zero.

For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
add that value to the other levels.  Add the necessary code in
sanitize_wm_latency() so that WaWmMemoryReadLatency is always applied
for Xe3p_LPD and beyond.

v2:
  - Rebased after addition of prep patch "drm/i915/wm: Reorder
    adjust_wm_latency() for Xe3_LPD" (dropped in v3).
v3:
  - Back to the simpler approach of doing the 'wm[0] = 0' step without
    modifying the rest of the code, and that inside
    sanitize_wm_latency(). (Matt Roper, Ville)

Bspec: 68986, 69126
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-20-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

0 files changed, 0 insertions, 0 deletions