diff options
author | Stephen Boyd <sboyd@kernel.org> | 2025-07-29 15:18:33 -0700 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-29 15:18:33 -0700 |
commit | e3abdd1870b7dcccf3447a78037217b95929587d (patch) | |
tree | 994780994e4dbcce8e32f665d0c519969288a6cb /tools/perf/util/scripting-engines/trace-event-python.c | |
parent | f7887ee4ee2b1fa2a538db4dbf3cec26538f317a (diff) | |
parent | b1712f94f7fcacf6b3dc4d9b73fd161bb3f2bb70 (diff) | |
parent | 2a5cebd0fcaf6567c16409c93fe4b0f287a11df9 (diff) | |
parent | c60b95389d0206a3a3c087c09113315e7084be3f (diff) | |
parent | 0b4ff5bc7d75553e243de5e2baf867c9beb63bef (diff) | |
parent | 8e766823592a4450f0405a96003642bde56bbb01 (diff) |
Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next
* clk-renesas: (42 commits)
clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
clk: renesas: r9a09g057: Add XSPI clock/reset
clk: renesas: r9a09g056: Add XSPI clock/reset
clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
clk: renesas: r9a09g057: Add support for xspi mux and divider
clk: renesas: r9a09g056: Add support for xspi mux and divider
clk: renesas: r9a09g077: Add RIIC module clocks
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
clk: renesas: r9a09g057: Add entries for the RSPIs
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
clk: renesas: rzv2h: Add missing include file
clk: renesas: rzv2h: Use devm_kmemdup_array()
clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
clk: renesas: r9a09g077: Add PCLKL core clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
...
* clk-samsung:
clk: samsung: exynosautov920: add block hsi2 clock support
dt-bindings: clock: exynosautov920: add hsi2 clock definitions
dt-bindings: clock: exynosautov920: sort clock definitions
clk: samsung: exynos850: fix a comment
clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD
* clk-spacemit:
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: mark K1 pll1_d8 as critical
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
* clk-allwinner:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
* clk-amlogic:
clk: amlogic: s4: remove unused data
clk: amlogic: drop clk_regmap tables
clk: amlogic: get regmap with clk_regmap_init
clk: amlogic: remove unnecessary headers
clk: amlogic: axg-audio: use the auxiliary reset driver