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2025-01-08arm64: dts: qcom: pmi8950: add LAB-IBB nodesNeil Armstrong
Add the PMI8950 LAB-IBB regulator nodes, with the PMI8998 compatible as fallback. The LAB-IBB regulators are used as panels supplies on existing phones or tablets. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241115-topic-sdm450-upstream-lab-ibb-v1-1-8a8e74befbfe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08arm64: dts: qcom: ipq5424: enable the download mode supportManikanta Mylavarapu
Enable support for download mode to collect RAM dumps in case of system crash, facilitating post mortem analysis. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204141416.1352545-3-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08arm64: dts: qcom: ipq5424: add scm nodeManikanta Mylavarapu
Add an scm node to interact with the secure world. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204133627.1341760-3-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08arm64: dts: ti: k3-am62a-wakeup: Configure ti-sysc for wkup_uart0Vibhore Vardhan
Similar to the TI K3-AM62x SoC commit ce27f7f9e328c8582a169f97f1466976561f1 ("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0"), The devices in the wkup domain are capable of waking up the system from suspend. We can configure the wkup domain devices in a generic way using the ti-sysc interconnect target module driver like we have done with the earlier TI SoCs. As ti-sysc manages the SYSCONFIG related registers independent of the child hardware device, the wake-up configuration is also set even if wkup_uart0 is reserved by sysfw. The wkup_uart0 device has interconnect target module register mapping like dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP block in the target module. The power domain and clock affects the whole interconnect target module. Note we change the functional clock name to follow the ti-sysc binding and use "fck" instead of "fclk". Also note that we need to disable the target module reset as noted by Markus. Otherwise the sysfw using wkup_uart0 can get confused on some devices leading to boot time issues such as mbox timeouts. Signed-off-by: Vibhore Vardhan <vibhore@ti.com> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> [d-gole@ti.com: Reworded the entire commit message] Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20241231-am62a-dt-ti-sysc-wkup-v1-1-a9b0d18a2649@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-j722s-evm: Enable PMICUdit Kumar
Add support for TPS6522x PMIC family on wakeup I2C0 bus. This device provides regulators (bucks and LDOs), along with GPIOs, and monitors SOC's MCU error signal. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250102103814.102499-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed supportDasnavis Sabiya
AM69 SK board has two stacked USB3 connectors: 1. USB3 (Stacked TypeA + TypeC) 2. USB3 TypeA Hub interfaced through TUSB8041. The board uses SERDES0 Lane 3 for USB3 IP. So update the SerDes lane info for PCIe and USB. Add the pin mux data and enable USB 3.0 support with its respective SERDES settings. Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20250108-am69sk-dt-usb-v3-1-bb4981534754@redhat.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-am625-beagleplay: Fix DP83TD510E reset timeFrancesco Valla
The reset deassert time for the DP83TD510E is incorrectly set to 60000us, while the datasheet states that the minimum time required after an hard reset is 30us (while 60ms is the time required for the Power-On Reset after supply stabilization). The error probably arose from the two timings being indicated by the same symbol (T2). Lower the required time to 35us, aligning it to the value required for the PHY to complete the reset AND to be able to accept the RMII master clock. This saves ~60ms on boot if the MDIO driver is built-in. Signed-off-by: Francesco Valla <francesco@valla.it> Link: https://lore.kernel.org/r/20250105162630.243899-1-francesco@valla.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-am642-hummingboard-t: Convert overlay to board dtsJosua Mayer
SolidRun HummingBoard-T has two options for M.2 connector, supporting either PCI-E or USB-3.1 Gen 1 - depending on configuration of a mux on the serdes lane. The required configurations in device-tree were modeled as overlays. The USB-3.1 overlay uses /delete-property/ to unset a boolean property on the usb controller limiting it to USB-2.0 by default. Overlays can not delete a property from the base dtb, therefore this overlay is at this time useless. Convert both overlays into full dts by including the base board dts. While the pcie overlay was functional, both are converted for a consistent user experience when selecting between the two mutually exclusive configurations. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Closes: https://lore.kernel.org/linux-devicetree/CAMuHMdXTgpTnJ9U7egC2XjFXXNZ5uiY1O+WxNd6LPJW5Rs5KTw@mail.gmail.com Fixes: bbef42084cc1 ("arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3") Signed-off-by: Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20250101-am64-hb-fix-overlay-v2-1-78143f5da28c@solid-run.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint ModeSiddharth Vadapalli
Add overlay to enable the PCIE0 instance of PCIe on AM69-SK in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20241205105041.749576-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint ModeSiddharth Vadapalli
Add overlay to enable the PCIE1 instance of PCIe on AM68-SK-Base-Board in Endpoint mode of operation. PCIE1 on AM68-SK-Base-Board supports x2 Lane operation unlike its counterpart on J721S2-EVM which supports x1 Lane. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20241205105041.749576-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint ModeSiddharth Vadapalli
Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint mode of operation. Additionally, in order to support both PCIE0 and PCIE1 in Endpoint Mode of operation, enable applying device-tree overlays on "k3-j721e-evm-pcie0-ep.dtb", thereby allowing the overlay for PCIE1 in Endpoint mode to be applied on the aforementioned DTB. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20241205105041.749576-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo"Siddharth Vadapalli
The list of "dtbs" should contain the resultant "dtb" formed by applying the "dtbo" overlay on the base "dtb", rather than the "dtbo" itself. Hence, change "k3-j7200-evm-pcie1-ep.dtbo" to "k3-j7200-evm-pcie1-ep.dtb" in the list of "dtbs". Fixes: f43ec89bbc83 ("arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20241205105041.749576-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-08arm64: dts: rockchip: enable hdmi out audio on wolfvision pf5Michael Riesch
Enable HDMI out audio on the WolfVision PF5 mainboard. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20241218-b4-wolfvision-pf5-update-v1-2-1d1959858708@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: fix num-channels property of wolfvision pf5 micMichael Riesch
The Rockchip RK3568 PDM block always considers stereo inputs. Therefore, the number of channels must be always an even number, even if a single mono microphone is attached. Fixes: 0be29f76633a ("arm64: dts: rockchip: add wolfvision pf5 mainboard") Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20241218-b4-wolfvision-pf5-update-v1-1-1d1959858708@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Enable the USB 3.0 port on NanoPi R6C/R6SAnton Kirilov
Enable the USB 3.0 port on FriendlyElec NanoPi R6C/R6S boards. Signed-off-by: Anton Kirilov <anton.kirilov@arm.com> Link: https://lore.kernel.org/r/20241219112532.482891-1-anton.kirilov@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add FRAM MB85RS128TY to rk3568-mecsbcDavid Jander
The board features a Fujitsu MB85RS128TY FRAM chip connected to spi0 CS 0. Add support for the MB85RS128TY to the device tree. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Link: https://lore.kernel.org/r/20241219-mb85rs128ty-mecsbc-v1-2-77a0e851ef19@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Remove unused i2c2 node from rk3568-mecsbcDavid Jander
One of the pins of i2c2 is actually in use as chip select 0 for spi0. The chip select 0 is used for an FRAM chip, which will be added in the next patch. Remove the i2c2 node from the rk3568-mecsbc device tree. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Link: https://lore.kernel.org/r/20241219-mb85rs128ty-mecsbc-v1-1-77a0e851ef19@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Fix PCIe3 handling for Edgeble-6TOPS ModulesJagan Teki
The Edgeble 6TOPS modules has configured the PCIe3.0 with - 2 lanes on Port1 of pcie3x2 controller for M.2 M-Key - 2 lanes on Port0 of pcie3x4 controller for B and E-Key The, current DT uses opposite controller nodes that indeed uses incorrect reset, regulator nodes. The configuration also uses refclk oscillator that need to enable explicitly in DT to avoid the probe hang on while reading DBI. So, this patch fixes all these essential issues and make this PCIe work properly. Issues fixed are, - Fix the associate controller nodes for M and B, E-Key - Fix the reset gpio handlings - Fix the regulator handlings and naming convensions - Support pcie_refclk oscillator Fixes: 92eaee21abbd ("arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key") Fixes: 5d85d4c7e03b ("arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key") Reported-by: Mitchell Ma <machuang@radxa.com> Co-developed-by: Mitchell Ma <machuang@radxa.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20241221151758.345257-1-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08ARM: dts: mediatek: mt7623: fix IR nodenameRafał Miłecki
Fix following validation error: arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dtb: cir@10013000: $nodename:0: 'cir@10013000' does not match '^ir(-receiver)?(@[a-f0-9]+)?$' from schema $id: http://devicetree.org/schemas/media/mediatek,mt7622-cir.yaml# Fixes: 91044f38dae7 ("arm: dts: mt7623: add ir nodes to the mt7623.dtsi file") Cc: linux-media@vger.kernel.org Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240617094634.23173-1-zajec5@gmail.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2025-01-08arm64: dts: rockchip: Add Radxa E52CFUKAUMI Naoki
Radxa E52C[1] is a compact network computer based on the Rockchip RK3582 SoC: - Dual Cortex-A76 and quad Cortex-A55 CPU - 5TOPS NPU - 2GB/4GB/8GB LPDDR4 RAM - 16GB/32GB/64GB on-board eMMC - microSD card slot - USB 3.0 Type-A HOST port - USB Type-C debug port - USB Type-C power port (5V only) - 2x 2.5GbE ports [1] https://radxa.com/products/network-computer/e52c Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241226024630.13702-3-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08dt-bindings: arm: rockchip: Add Radxa E52CFUKAUMI Naoki
Add devicetree binding for the Radxa E52C. Radxa E52C is a compact network computer based on the Rockchip RK3582 SoC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241226024630.13702-2-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add BigTreeTech CB2 and Pi2Ivan Sergeev
BigTreeTech CB2 and Pi2 share a lot of hardware configuration, so a common dtsi file was used to define common nodes and properties. This is similar to how BigTreeTech CB1 and Pi are implemented. Signed-off-by: Ivan Sergeev <ivan8215145640@gmail.com> Link: https://lore.kernel.org/r/20250106-bigtreetech-cb2-v7-2-565567e2c0a4@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08dt-bindings: arm: rockchip: Add BigTreeTech CB2 and Pi2Ivan Sergeev
BigTreeTech CB2 and Pi2 are Rockchip RK3566 based boards Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ivan Sergeev <ivan8215145640@gmail.com> Link: https://lore.kernel.org/r/20250106-bigtreetech-cb2-v7-1-565567e2c0a4@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Enable USB 3.0 ports on orangepi-5-plusChen-Yu Tsai
The Orange Pi 5 Plus has its first USB 3.0 interface on the SoC wired directly to the USB type C port next to the MASKROM button, and the second interface wired to a USB 3.0 hub which in turn is connected to the USB 3.0 host ports on the board, as well as the USB 2.0 connection on the M.2 E-key slot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20241220161240.109253-1-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add H96 Max V58 TV Box based on RK3588 SoCAlexey Charkov
H96 Max V58 is a compact Rockchip RK3588 based device that ships with Android and is meant for use as a TV connected media box. Its hardware includes: - Rockchip RK3588 SoC with a small aluminium heatsink - 4GB or 8GB LPDDR4 RAM - 32GB or 64GB eMMC 5.1 storage (HS400) - Onboard AP6275P wireless module providing 802.11ax 2x2 MIMO WiFi over PCIe connection and Bluetooth 5.3 over UART with two external detachable antennas - 1x GbE using the onboard GMAC and an RTL8211F PHY - 1x USB 2.0 Type-A (also serves as the Maskrom port) - 1x USB 3.0 Type-A - 1x HDMI 2.1 output - 1x optical SPDIF output - LED line display ("88:88" digits plus icons) driven by an FD6551 IC connected over bitbanged I2C (not yet enabled here) - GPIO connected CIR receiver - Single Rockchip RK806-1 PMIC - 12x onboard ambient LEDs lighting up the bottom of the device - 5v DCIN using a standard round 5.5mm connector Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250108-rk3588-h96-max-v58-v2-3-522301b905d6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08dt-bindings: arm: rockchip: Add H96 Max V58 TV boxAlexey Charkov
Add Devicetree binding for H96 Max V58: a compact Rockchip RK3588 based device that ships with Android and is meant for use as a TV connected media box. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250108-rk3588-h96-max-v58-v2-1-522301b905d6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add rk3576 evb1 boardKever Yang
RK3576 EVB1 board features: - Rockchip RK3576 - PMIC: RK806-2x2pcs+DiscretePower - RAM: LPDDR4/4x 2pcsx 32bit - ROM: eMMC5.1 + UFS - LAN x 2 - HDMI TX - SD card slot - PCIe2 slot Add support for pmic, eMMC, SD-card, ADC-KEY, PCIE and GMAC. NOTE: The board has a hardware mux design for - PCIe slot(pcie1) - USB3 host(usb_drd1_dwc3) and default state is switch to USB3. To enable PCIe slot: - hardware: Switch the mux to PCIe side; - dts: disable usb_drd1_dwc3 and enable pcie1; Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250107074911.550057-8-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08dt-bindings: arm: rockchip: Add rk3576 evb1 boardKever Yang
Add device tree documentation for rk3576-evb1-v10. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250107074911.550057-7-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08dt-bindings: arm: rockchip: Sort for boards not in correct orderKever Yang
The board entries should be sort in correct order by the description string. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250107074911.550057-6-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: add usb related nodes for rk3576Frank Wang
This adds USB and USB-PHY related nodes for RK3576 SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250107074911.550057-5-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add rk3576 naneng combphy nodesKever Yang
rk3576 has two naneng combo phys: - combophy0 is used for one of pcie and sata; - combophy1 is used for one of pcie, sata and usb3; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250107074911.550057-2-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: marvell: drop additional phy-names for sataFrank Wunderlich
Commit facbe7092f8a ("arm64: dts: marvell: Drop undocumented SATA phy names") drops some phy-names from devicetrees but misses some. Drop them too. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08arm64: dts: marvell: only enable complete sata nodesFrank Wunderlich
The ahci-platform binding requires phys/target-supply property. After converting the binding to yaml the following files reporting "'anyOf' conditional failed" on sata@540000: sata-port@0 armada-7040-db.dts armada-8040-clearfog-gt-8k.dts armada-8040-mcbin.dts armada-8040-mcbin-singleshot.dts cn9130-db.dts cn9130-db-B.dts cn9131-db.dts cn9131-db-B.dts cn9132-db.dts cn9132-db-B.dts the following files reporting 'anyOf' conditional failed on sata@540000: sata-port@1 cn9132-db.dts cn9132-db-B.dts cn9130-crb-B.dts 'phys' is a required property 'target-supply' is a required property >From schema: Documentation/devicetree/bindings/ata/ahci-platform.yaml This is caused by defining sata-ports incomplete in armada-cp11x.dtsi and overriding only a subset of ports with the needed phys/target-supply property. Fix this by disabling the node-templates and enabling the needed nodes. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08arm64: dts: marvell: cn9131-cf-solidwan: fix cp1 comphy linksJosua Mayer
Marvell CN913x platforms use common phy framework for configuring and linking serdes lanes according to their usage. Each CP (X) features 5 serdes lanes (Y) represented by cpX_comphyY nodes. CN9131 SolidWAN uses CP1 serdes lanes 3 and 5 for eth1 and eth2 of CP1 respectively. Devicetree however wrongly links from these ports to the comphy of CP0. Replace the wrong links to cp0_comphy with cp1_comphy inside cp1_eth1, cp1_eth2. Fixes: 1280840d2030 ("arm64: dts: add description for solidrun cn9131 solidwan board") Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-07arm64: dts: qcom: sm8250: Fix interrupt types of camss interruptsVladimir Zapolskiy
Qualcomm IP catalog says that all CAMSS interrupts is edge rising, fix it in the CAMSS device tree node for sm8250 SoC. Fixes: 30325603b910 ("arm64: dts: qcom: sm8250: camss: Add CAMSS block definition") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20241127122950.885982-7-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sdm845: Fix interrupt types of camss interruptsVladimir Zapolskiy
Qualcomm IP catalog says that all CAMSS interrupts is edge rising, fix it in the CAMSS device tree node for sdm845 SoC. Fixes: d48a6698a6b7 ("arm64: dts: qcom: sdm845: Add CAMSS ISP node") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20241127122950.885982-6-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sc8280xp: Fix interrupt type of camss interruptsVladimir Zapolskiy
Qualcomm IP catalog says that all CAMSS interrupts are edge rising, fix it in the CAMSS device tree node for sc8280xp SoC. Fixes: 5994dd60753e ("arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241127122950.885982-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300-ride: Enable USB controllersKrishna Kurapati
Enable primary USB controller on QCS8300 Ride platform. The primary USB controller is made "peripheral", as this is intended to be connected to a host for debugging use cases. For using the controller in host mode, changing the dr_mode and adding appropriate pinctrl nodes to provide vbus would be sufficient. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241114055152.1562116-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300: Add support for usb nodesKrishna Kurapati
Add support for USB controllers on QCS8300. The second controller is only High Speed capable. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241114055152.1562116-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300: Add support for clock controllersImran Shaik
Add support for GPU, Video, Camera and Display clock controllers on Qualcomm QCS8300 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20241114-qcs8300-mm-cc-dt-patch-v1-1-7a974508c736@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sm8450: Add coresight nodesMao Jinlong
Add coresight components on Qualcomm SM8450 Soc. The components include TMC ETF/ETR, ETE, STM, TPDM, CTI. Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Link: https://lore.kernel.org/r/20250107090031.3319-3-quic_jinlmao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regionsManivannan Sadhasivam
For both the controller instances, size of the 'addr_space' region should be 0x1fe00000 as per the hardware memory layout. Otherwise, endpoint drivers cannot request even reasonable BAR size of 1MB. Cc: stable@vger.kernel.org # 6.11 Fixes: c5f5de8434ec ("arm64: dts: qcom: sa8775p: Add ep pcie1 controller node") Fixes: 1924f5518224 ("arm64: dts: qcom: sa8775p: Add ep pcie0 controller node") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20241231130224.38206-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs615-ride: Enable UFS nodeSayali Lokhande
Enable UFS on the Qualcomm QCS615 Ride platform. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Xin Liu <quic_liuxin@quicinc.com> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> Link: https://lore.kernel.org/r/20241216095439.531357-4-quic_liuxin@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs615: add UFS nodeSayali Lokhande
Add the UFS Host Controller node and its PHY for QCS615 SoC. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Co-developed-by: Xin Liu <quic_liuxin@quicinc.com> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241216095439.531357-3-quic_liuxin@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: ipq5424: Add USB controller and phy nodesVaradarajan Narayanan
The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 can connect to either of USB2.0 or USB3.0 phy and operate in the respective mode. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241118052839.382431-7-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controllerVaradarajan Narayanan
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on IPQ5424 SoCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241121051935.1055222-4-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-08ARM: dts: aspeed: yosemite4: adjust secondary flash namePatrick Williams
Meta (Facebook) has a preference for all of our secondary flash chips to be labelled "alt-bmc" for consistency of userspace tools deal with updates. Bletchley, Harma, Minerva, and Catalina all follow this convention but for some reason Yosemite4 is different. Adjust the label in the dts to match the other platforms. Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Link: https://patch.msgid.link/20250107162726.232402-1-patrick@stwcx.xyz Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-01-07ARM: dts: ti/omap: omap3-gta04: use proper touchscreen propertiesAndreas Kemnade
Specify the dimensions of the touchscreen propertly so that no userspace configuration is needed for it. Tested with x11 and weston on Debian bookworm. What is in now is some debris from earlier tries to handle scaling in kernel: https://lore.kernel.org/linux-input/cover.1482936802.git.hns@goldelico.com/ Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20241205204413.2466775-3-akemnade@kernel.org Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-01-07ARM: dts: ti: am437x-l4: remove autoidle for UARTJudith Mendez
According to the TRM [0] in 21.5.1.42 UART_SYSC Register, the autoidle bit should not be set for UART, so remove the appropriate SYSC_OMAP2_AUTOIDLE flag. [0] https://www.ti.com/lit/ug/spruhl7i/spruhl7i.pdf Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Sukrut Bellary <sbellary@baylibre.com> Link: https://lore.kernel.org/r/20241220223523.2125278-1-jm@ti.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-01-07ARM: dts: ti/omap: gta04: fix pm issues caused by spi moduleAndreas Kemnade
Despite CM_IDLEST1_CORE and CM_FCLKEN1_CORE behaving normal, disabling SPI leads to messages like when suspending: Powerdomain (core_pwrdm) didn't enter target state 0 and according to /sys/kernel/debug/pm_debug/count off state is not entered. That was not connected to SPI during the discussion of disabling SPI. See: https://lore.kernel.org/linux-omap/20230122100852.32ae082c@aktux/ The reason is that SPI is per default in slave mode. Linux driver will turn it to master per default. It slave mode, the powerdomain seems to be kept active if active chip select input is sensed. Fix that by explicitly disabling the SPI3 pins which used to be muxed by the bootloader since they are available on an optionally fitted header which would require dtb overlays anyways. Fixes: a622310f7f01 ("ARM: dts: gta04: fix excess dma channel usage") CC: stable@vger.kernel.org Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20241204174152.2360431-1-andreas@kemnade.info Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit (git 2.34.1) at 2025-09-09 02:09:40 +0000