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2025-06-10arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"Rob Herring (Arm)
The default interrupt parent is a parent node containing "#interrupt-cells", so an explicit "interrupt-parent" is not necessary. Fixes these dtschema warnings: (arm,gic-400): v2m@70000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@60000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@50000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@40000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@30000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@20000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@10000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@0: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250609203705.2852500-1-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: broadcom: Add overlay for RP1 deviceAndrea della Porta
Define the RP1 node in an overlay. The inclusion tree is as follow (the arrow points to the includer): rp1.dtso ^ | rp1-common.dtsi ----> rp1-nexus.dtsi Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-10-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 nodeAndrea della Porta
Add the fully populated DTS for RaspberryPi 5 which includes the RP1 node definition. The inclusion tree is as follow (the arrow points to the includer): rp1-common.dtsi ----> rp1-nexus.dtsi ----> bcm2712-rpi-5-b.dts ^ | bcm2712-rpi-5-b-ovl-rp1.dts This is designed to maximize the compatibility with downstream DT while ensuring that a fully defined DT (one which includes the RP1 node as opposed to load it from overlay at runtime) is present since early boot stage. Since the preferred board DT is the fully populated one, name it bcm2712-rpi-5-b.dts and move the previous one into bcm2712-rpi-5-b-ovl-rp1.dts. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/20250529135052.28398-9-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5Andrea della Porta
The RP1 found on Raspberry Pi 5 board needs an external crystal at 50MHz. Add clk_rp1_xosc node to provide that. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-8-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: rp1: Add support for RaspberryPi's RP1 deviceAndrea della Porta
RaspberryPi RP1 is a multi function PCI endpoint device that exposes several subperipherals via PCI BAR. Add a dtb overlay that will be compiled into a binary blob and linked in the RP1 driver. This overlay offers just minimal support to represent the RP1 device itself, the sub-peripherals will be added by future patches. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-6-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm63158: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM63158 based on the vendor files 63158_map_part.h and 63158_intr.h from the "bcmopen-consumer" code drop. The DTSI file has clearly been authored for the B0 revision of the SoC: there is an earlier A0 version, but this has the UARTs in the legacy PERF memory space, while the B0 has opened a new peripheral window at 0xff812000 for the three UARTs. It also has a designated AHB peripheral area at 0xff810000 where the DMA resides, the peripheral range window fits these two peripheral groups. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-12-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm6858: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000. Extend the peripheral window range to 0x400000 and add the DMA controller at offset 0x59000. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM6858 based on the vendor files 6858_map_part.h and 6858_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-11-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm6856: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000. Extend the BCM6856 the PERF window to 0x400000 and add the DMA block at offset 0x59000. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM6856 based on the vendor files 6856_map_part.h and 6856_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-10-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm4908: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000, we extend the peripheral bus range to 0x400000 to cover this area. Add the watchdog, remaining GPIO blocks, RNG, and DMA blocks for the BCM4908 based on the vendor files 4908_map_part.h and 4908_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 320 possible GPIOs due to having 10 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-9-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-05-09Merge tag 'arm-soc/for-6.16/devicetree-arm64' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.16, please pull the following: - Stanimir adds and enables the PCIe root complex Device Tree nodes present on the Raspberry Pi 5 - Rob updates the BCM2712 L2 cache node names to use a more comforming name * tag 'arm-soc/for-6.16/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodes arm64: dts: broadcom: bcm2712: Add PCIe DT nodes Link: https://lore.kernel.org/r/20250505165810.1948927-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-05arm64: dts: bcm: Add reference to RPi 2 (2nd rev)Stefan Wahren
This adds a reference to the dts of the Raspberry Pi 2 (2nd rev), so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250418143307.59235-4-wahrenst@gmx.net Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-04-11arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node namesRob Herring (Arm)
There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/all/20250410-dt-cpu-schema-v2-2-63d7dc9ddd0a@kernel.org/ Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-04-07arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodesStanimir Varbanov
Enable pcie1 and pcie2 DT nodes. Pcie1 is used for the extension connector and pcie2 is used for RP1 south-bridge. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Link: https://lore.kernel.org/r/20250120130119.671119-12-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-04-07arm64: dts: broadcom: bcm2712: Add PCIe DT nodesStanimir Varbanov
Add PCIe devicetree nodes, plus needed reset and mip MSI-X controllers. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Link: https://lore.kernel.org/r/20250120130119.671119-11-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-02-25arm64: dts: bcm2712: PL011 UARTs are actually r1p5Phil Elwell
The ARM PL011 UART instances in BCM2712 are r1p5 spec, which means they have 32-entry FIFOs. The correct periphid value for this is 0x00341011. Thanks to N Buchwitz for pointing this out. Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250223125614.3592-3-wahrenst@gmx.net Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for Raspberry Pi 5") Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-01-24Merge tag 'soc-dt-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "We see the addition of eleven new SoCs, including a total of sixx arm64 chips from Qualcomm alone. Overall, the Qualcomm platforms once again make up the majority of all changes, after a couple of quieter releases. The new SoCs in this branch are: - Microchip sama7d65 is a new 32-bit embedded chip with a single Cortex-A7 and the current high end of the old Atmel SoC line. - Samsung Exynos 9810 is a mobile phone chip used in some older phones like the Samsung Galaxy S9 - Renesas R-Car V4H ES3.0 (R8A779G3) is an updated version of the V4H (R8A779G0) low-power automotive SoC - Renesas RZ/G3E (R0A09G047) is a family of embedded chips using Cortex-A55 cores - Qualcomm Snapdragon 8 Elite (SM8750) is a new phone chip based on Qualcomm's Oryon CPU cores. - Qualcomm Snapdragon AR2 (SAR2130P) is a SoC for augmented reality glasses. - Qualcomm IQ6 (QCS610) and IQ8 (QCS8300) are two industrial IOT platforms. - Snapdragon 425 (MSM8917) is a mobile phone SoC from 2016 - Qualcomm IPQ5424 is a Wi-Fi 7 networking chip All of the above are part of already supported SoC families that only need new devicetree files. Two additional SoCs in new families are part of a separate branch. There are 48 new machines in total, including six arm32 ones based on aspeed. broadcom, microchip and st SoCs all using Cortex-A7 cores, and a single risc-v board, the Banana Pi R3. The remaining ones use arm64 chips from Broadcom, Samsung, NXP, Mediatek, Qualcomm, Renesas and Rockchips and cover development boards, phones, laptops, industrial machines routers. A lot of ongoing work is for cleaning up build time warnings and other issues, in addition to the new machines and added features" * tag 'soc-dt-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (619 commits) arm64: tegra: Fix Tegra234 PCIe interrupt-map arm64: dts: qcom: x1e80100-romulus: Update firmware nodes arm64: dts: rockchip: add DTs for Firefly ITX-3588J and its Core-3588J SoM dt-bindings: arm: rockchip: Add Firefly ITX-3588J board arm64: dts: rockchip: Add Orange Pi 5 Max board dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Max arm64: dts: rockchip: refactor common rk3588-orangepi-5.dtsi arm64: dts: rockchip: add WLAN to rk3588-evb1 controller arm64: dts: rockchip: increase gmac rx_delay on rk3399-puma arm64: dts: rockchip: Delete redundant RK3328 GMAC stability fixes arm64: tegra: Disable Tegra234 sce-fabric node arm64: tegra: Fix typo in Tegra234 dce-fabric compatible arm64: tegra: Fix DMA ID for SPI2 arm64: dts: qcom: msm8916-samsung-serranove: Add display panel arm64: dts: qcom: sm8650: Add 'global' interrupt to the PCIe RC nodes arm64: dts: qcom: sm8550: Add 'global' interrupt to the PCIe RC nodes arm64: dts: qcom: Remove unused and undocumented properties arm64: dts: qcom: sdm450-lenovo-tbx605f: add DSI panel nodes arm64: dts: qcom: pmi8950: add LAB-IBB nodes arm64: dts: qcom: ipq5424: enable the download mode support ...
2024-12-17arm64: dts: bcm4908: nvmem-layout conversionRosen Penev
nvmem-layout is a more flexible replacement for nvmem-cells. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://lore.kernel.org/r/20241203233632.184861-1-rosenp@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: bcmbca: bcm4908: Add DT for Zyxel EX3510-BSam Edwards
Zyxel EX3510-B is a WiFi 6 capable home gateway (family) based on the BCM4906 SoC, with 512MiB of RAM and 512MiB of NAND flash. WiFi support consists of a BCM6710 and a BCM6715 attached to separate PCIe buses. Add an initial devicetree for this system, with support for: - Onboard UART (per base dtsi) - USB (2.0 only; superspeed devices are treated as high-speed due to an unknown cause) - Both buttons (rear reset, front WPS) - Almost all LEDs: - Power (red/green) - Internet (red/green) - WAN (green) - LAN (green; anode is connected to GPIO 13 so currently nonfunctioning) - USB (green) - WPS button (red/green) - Absent in DT: There are 2.4GHz/5.0GHz WiFi status LEDs connected to the WiFi chips instead of the SoC. - NAND flash - Embedded Ethernet switch - Factory-programmed Ethernet MAC address WiFi cannot be enabled at this time due to Linux lacking drivers for both the PCIe controllers and the PCIe WiFi peripherals. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20241009215454.1449508-3-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: bcmbca: bcm4908: Protect cpu-release-addrSam Edwards
The `cpu-release-addr` property is relevant only when the "spin-table" enable method is used. It is the physical address where the bootloader expects Linux to write the secondary CPU entry point's physical address. On this platform, only the CFE bootloader uses this method: U-Boot uses PSCI instead. CFE actually walks the FDT to learn this address, so we're free to put it wherever we want. We only need to make sure that it goes in a reserved-memory block so that writing to it during early boot does not risk conflicting with an unrelated memory allocation: this was not done. Since the previous patch reserved the first page of memory for CFE's secondary-CPU init stub, which is actually much smaller than a page, just put this address at the end of that page and it shall be so protected. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20241005050155.61103-3-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: bcmbca: bcm4908: Reserve CFE stub areaSam Edwards
The CFE bootloader places a stub program in the first page of physical memory to hold the secondary CPUs until the boot CPU writes the release address, but does not splice a /reserved-memory node into the FDT to protect it. If Linux overwrites this program before execution reaches smp_prepare_cpus(), the secondary CPUs may become inaccessible. This is only a problem with CFE, and then only until the secondary CPUs are brought online. Ideally, there would be some hypothetical mechanism we could use to indicate that this area of memory is sensitive only during boot. But as there is none, and since it is such a small amount of memory, it is easiest to reserve it unconditionally. Therefore, add a /reserved-memory node to bcm4908.dtsi to protect the first 4KiB of physical memory. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20241005050155.61103-2-CFSworks@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Remove unused and undocumented propertiesRob Herring (Arm)
Remove properties which are both unused in the kernel and undocumented. Most likely they are leftovers from downstream. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241115193854.3624123-1-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Add DT for D-step version of BCM2712Dave Stevenson
The D-Step has some minor variations in the hardware, so needs matching changes to DT. Add a new DTS file that modifies the existing (C-step) devicetree. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-36-35efa83c8fc0@raspberrypi.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Add display pipeline support to BCM2712Dave Stevenson
Adds the HVS and associated hardware blocks to support the HDMI and writeback connectors on BCM2712 / Pi5. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-35-35efa83c8fc0@raspberrypi.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Add firmware clocks and power nodes to Pi5 DTDave Stevenson
BCM2712 still uses the firmware clocks and power drivers, so add them to the base device tree. The brcm,bcm2836-l1-intc controller isn't used on this platform. It is used on 32-bit kernels for the smp_boot_secondary hook, but BCM2712 can't run a 32-bit kernel. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20241025-drm-vc4-2712-support-v2-34-35efa83c8fc0@raspberrypi.com Link: https://lore.kernel.org/r/20241212-dt-bcm2712-fixes-v3-7-44a7f3390331@raspberrypi.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-12-17arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5Willow Cunningham
Set the cache-line-size parameter of the L2 cache for each core to the correct value of 64 bytes. Previously, the L2 cache line size was incorrectly set to 128 bytes for the Broadcom BCM2712. This causes validation tests for the Performance Application Programming Interface (PAPI) tool to fail as they depend on sysfs accurately reporting cache line sizes. The correct value of 64 bytes is stated in the official documentation of the ARM Cortex A-72, which is linked in the comments of arm64/boot/dts/broadcom/bcm2712.dtsi as the source for cache-line-size. Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for Raspberry Pi 5") Signed-off-by: Willow Cunningham <willow.e.cunningham@maine.edu> Link: https://lore.kernel.org/r/20241007212954.214724-1-willow.e.cunningham@maine.edu Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-08-13ARM: dts: bcm2837/bcm2712: adjust local intc node namesStefan Wahren
After converting the bcm2836-l1-intc DT binding to YAML, the DT schema checks gave warnings like: 'local_intc@40000000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' So fix them accordingly. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20240812200358.4061-4-wahrenst@gmx.net Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-07-29arm64: dts: broadcom: Add minimal support for Raspberry Pi 5Andrea della Porta
The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/874589f6c621036620cca944986e5be7238b4784.1717061147.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-05-02arm64: dts: Add/fix /memory node unit-addressesRob Herring
'/memory' nodes always have a 'reg' property, and therefore should have a unit-address with just plain hex (i.e. no commas). Fix all the arm64 '/memory' nodes. It's possible that some bootloader depends on /memory (arm32 ATAG to DT code does for example). If so, the memory node should be commented with that requirement. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Chanho Min <chanho.min@lge.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240430191856.874600-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-30Merge tag 'arm-soc/for-6.10/devicetree-arm64' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.10, please pull the following: - Rafal moves the "brcm,wp-not-connected" property from the individual board DTSes to the SoC' DTSI since all boards a designed the same way * tag 'arm-soc/for-6.10/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connected Link: https://lore.kernel.org/r/20240429213703.2327834-3-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-29arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usageRob Herring
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-02arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connectedRafał Miłecki
Every described BCM4908 board has WP pin not connected. This caused problems for drivers since day 0 but there was no property to describe that properly. Projects like OpenWrt were modifying Linux driver to deal with it. It's not clear if that is hardware limitation or just reference design being copied over and over but this applies to all known / supported BCM4908 boards. Handle it by marking WP as not connected by default. Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240328093710.28206-1-zajec5@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-03-19Merge tag 'soc-late-6.9' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These are changes that for some reason ended up not making it into the first four branches but that should still make it into 6.9: - A rework of the omap clock support that touches both drivers and device tree files - The reset controller branch changes that had a dependency on late bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the drivers branch - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree changes that got delayed and needed some extra time in linux-next for wider testing" * tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits) soc: fsl: dpio: fix kcalloc() argument order bus: ts-nbus: Improve error reporting bus: ts-nbus: Convert to atomic pwm API riscv: dts: starfive: jh7110: Add camera subsystem nodes ARM: bcm: stop selecing CONFIG_TICK_ONESHOT ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift clk: ti: Improve clksel clock bit parsing for reg property clk: ti: Handle possible address in the node name dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID reset: Instantiate reset GPIO controller for shared reset-gpios reset: gpio: Add GPIO-based reset controller cpufreq: do not open-code of_phandle_args_equal() of: Add of_phandle_args_equal() helper reset: simple: add support for Sophgo SG2042 dt-bindings: reset: sophgo: support SG2042 riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks ARM: brcmstb: Add debug UART entry for 74165 ...
2024-03-15Merge tag 'mtd/for-6.9' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "MTD: - The Carillo Ranch driver has been removed - Top level mtd bindings have received a couple of improvements (references, selects) - The ssfdc driver received few minor adjustments - The usual load of misc/small improvements and fixes Raw NAND: - The main series brought is an update of the Broadcom support to support all BCMBCA SoCs and their specificity (ECC, write protection, configuration straps), plus a few misc fixes and changes in the main driver. Device tree updates are also part of this PR, initially because of a misunderstanding on my side. - The STM32_FMC2 controller driver is also upgraded to properly support MP1 and MP25 SoCs. - A new compatible is added for an Atmel flavor. - Among all these feature changes, there is as well a load of continuous read related fixes, avoiding more corner conditions and clarifying the logic. Finally a few miscellaneous fixes are made to the core, the lpx32xx_mlc, fsl_lbc, Meson and Atmel controller driver, as well as final one in the Hynix vendor driver. SPI-NAND: - The ESMT support has been extended to match 5 bytes ID to avoid collisions. Winbond support on its side receives support for W25N04KV chips. SPI NOR: - SPI NOR gets the non uniform erase code cleaned. We stopped using bitmasks for erase types and flags, and instead introduced dedicated members. We then passed the SPI NOR erase map to MTD. Users can now determine the erase regions and make informed decisions on partitions size. - An optional interrupt property is now described in the bindings" * tag 'mtd/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (50 commits) mtd: rawnand: Ensure continuous reads are well disabled mtd: rawnand: Constrain even more when continuous reads are enabled mtd: rawnand: brcmnand: Add support for getting ecc setting from strap mtd: rawnand: brcmnand: fix sparse warnings mtd: nand: raw: atmel: Fix comment in timings preparation mtd: rawnand: Ensure all continuous terms are always in sync mtd: rawnand: Add a helper for calculating a page index mtd: rawnand: Fix and simplify again the continuous read derivations mtd: rawnand: hynix: remove @nand_technology kernel-doc description dt-bindings: atmel-nand: add microchip,sam9x7-pmecc mtd: rawnand: brcmnand: Support write protection setting from dts mtd: rawnand: brcmnand: Add BCMBCA read data bus interface mtd: rawnand: brcmnand: Rename bcm63138 nand driver arm64: dts: broadcom: bcmbca: Update router boards arm64: dts: broadcom: bcmbca: Add NAND controller node ARM: dts: broadcom: bcmbca: Add NAND controller node mtd: spi-nor: core: correct type of i mtd: spi-nor: core: set mtd->eraseregions for non-uniform erase map mtd: spi-nor: core: get rid of SNOR_OVERLAID_REGION flag mtd: spi-nor: core: get rid of SNOR_LAST_REGION flag ...
2024-03-15arm64: dts: broadcom: bcmbca: Update router boardsWilliam Zhang
Enable the nand controller and add WP pin connection property in actual board dts as they are board level properties now that they are disabled and moved out from SoC dtsi. Also remove the unnecessary brcm,nand-has-wp property from AC5300 board. This property is only needed for some old controller that this board does not apply. Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-10-william.zhang@broadcom.com
2024-03-15arm64: dts: broadcom: bcmbca: Add NAND controller nodeWilliam Zhang
Add support for Broadcom STB NAND controller in BCMBCA ARMv8 chip dts files. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: David Regan <dregan@broadcom.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-9-william.zhang@broadcom.com
2024-03-11Merge tag 'arm-soc/for-6.9/devicetree-arm64' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/late This pull request contains Broadcom ARM64-based SoCs changes for 6.9, please pull the following: - Rafal defines a proper NVMEM layout for the Asus GT-AC5300 router and removes some invalid Device Tree properties pertaining to the Ethernet switch on bcm4908 * tag 'arm-soc/for-6.9/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cells arm64: dts: broadcom: bcmbca: bcm4908: use NVMEM layout for Asus GT-AC5300 Link: https://lore.kernel.org/r/20240307200441.2151734-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-20arm64: dts: Fix dtc interrupt_provider warningsRob Herring
The dtc interrupt_provider warning is off by default. Fix all the warnings so it can be enabled. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> # Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> #Broadcom Acked-by: Chanho Min <chanho.min@lge.com> Link: https://lore.kernel.org/r/20240213-arm-dt-cleanups-v1-3-f2dee1292525@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-29arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cellsRafał Miłecki
Ethernet switch does not have addressable subnodes. This fixes: arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dtb: ethernet-switch@0: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml# Fixes: 527a3ac9bdf8 ("arm64: dts: broadcom: bcm4908: describe internal switch") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240111115636.12095-1-zajec5@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-01-29arm64: dts: broadcom: bcmbca: bcm4908: use NVMEM layout for Asus GT-AC5300Rafał Miłecki
Defining NVMEM cells as direct subnodes is deprecated since commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout"). Use new syntax based on NVMEM layout. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240111115617.12072-1-zajec5@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2023-10-18arm/arm64: dts: Removed undocumented and unused "pl022,hierarchy" propertyRob Herring
The "pl022,hierarchy" is not documented, all instances use are 0 and isn't handled in the kernel driver, so let's just remove it. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20230928190859.1072420-1-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-29arm64: dts: use capital "OR" for multiple licenses in SPDXKrzysztof Kozlowski
Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> # Broadcom Link: https://lore.kernel.org/r/20230823085146.113562-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-07-12arm64: dts: broadcom: add missing space before {Krzysztof Kozlowski
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230705150108.293999-2-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-01arm64: dts: broadcom: Enable device-tree overlay support for RPi devicesAurelien Jarno
Add the '-@' DTC option for the Raspberry Pi devices. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (for instance from the firmware or the bootloader) on these devices. The Rasbperry Pi devices are well known for their GPIO header, that allow various "HATs" or other modules do be connected and this enables users to create out-of-tree device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB by ~40%. For example, with v6.4-rc1 increase in size is as follows: bcm2711-rpi-400.dtb 27556 -> 38141 bytes bcm2711-rpi-4-b.dtb 27484 -> 38069 bytes bcm2711-rpi-cm4-io.dtb 27373 -> 38076 bytes bcm2837-rpi-3-a-plus.dtb 14930 -> 20713 bytes bcm2837-rpi-3-b.dtb 15107 -> 20979 bytes bcm2837-rpi-3-b-plus.dtb 15463 -> 21443 bytes bcm2837-rpi-cm3-io3.dtb 14429 -> 20098 bytes bcm2837-rpi-zero-2-w.dtb 14781 -> 20524 bytes Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Link: https://lore.kernel.org/r/20220410225940.135744-2-aurelien@aurel32.net [ukleinek: rebased to v6.4, replaced by a single assignment to DTC_FLAGS] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2023-05-25arm64: dts: broadcom: Unify pinctrl-single pin group nodes for stingrayTony Lindgren
We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Let's also correct the pinctrl controller #size-cells to 0 while at it. Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20230523065236.14524-1-tony@atomide.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2023-05-08arm64: dts: broadcom: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: bcm94908.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230421223208.115555-1-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2023-03-14arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB LED triggersRafał Miłecki
This device has 2 USB LEDs meant to be triggered by devices in relevant USB ports. While at it fix typo in USB LED name. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2023-03-14arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB LED triggersRafał Miłecki
This device has 2 USB LEDs meant to be triggered by devices in relevant USB ports. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2023-03-14arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB portsRafał Miłecki
BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often have LEDs indicating state of selected USB ports. Describe those SoC USB ports to allow using them as LED trigger sources. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2023-03-14arm64: dts: broadcom: bcmbca: bcm4908: fix procmon nodenameRafał Miłecki
This fixes: arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: syscon@280000: $nodename:0: 'syscon@280000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: schemas/simple-bus.yaml Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/all/20230228144400.21689-3-zajec5@gmail.com/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
generated by cgit (git 2.34.1) at 2025-08-03 15:54:04 +0000