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path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
2025-04-08clk: renesas: rzv2h: Rename PLL field macros for consistencyLad Prabhakar
2025-04-08clk: renesas: rzv2h: Add support for enabling PLLsLad Prabhakar
2025-04-08clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`Lad Prabhakar
2025-04-08clk: renesas: rzv2h: Refactor PLL configuration handlingLad Prabhakar
2025-03-06clk: renesas: r9a09g047: Add clock and reset signals for the TSU IPJohn Madieu
2025-03-06clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1Biju Das
2025-03-04clk: renesas: r7s9210: Distinguish clocks by clock typeGeert Uytterhoeven
2025-03-04clk: renesas: rzg2l: Remove unneeded nullify checksGeert Uytterhoeven
2025-03-04clk: renesas: cpg-mssr: Remove obsolete nullify checkGeert Uytterhoeven
2025-03-04clk: renesas: r9a09g057: Add entries for the DMACsFabrizio Castro
2025-02-20clk: renesas: r9a09g047: Add CANFD clocks and resetsBiju Das
2025-02-20clk: renesas: r9a09g047: Add CRU0 clocks and resetsTommaso Merciai
2025-02-18clk: renesas: rzv2h: Update error messageLad Prabhakar
2025-02-18clk: renesas: rzg2l: Update error messageLad Prabhakar
2025-02-03clk: renesas: r9a09g047: Add ICU clock/resetBiju Das
2025-02-03clk: renesas: r9a07g043: Fix HP clock source for RZ/FiveLad Prabhakar
2025-02-03clk: renesas: r9a09g047: Add SDHI clocks/resetsBiju Das
2025-02-03clk: renesas: r8a779h0: Add VSPX clockNiklas Söderlund
2025-02-03clk: renesas: r8a779h0: Add FCPVX clockNiklas Söderlund
2025-02-03clk: renesas: r8a08g045: Check the source of the CPU PLL settingsClaudiu Beznea
2025-02-03clk: renesas: r9a09g047: Add WDT clocks and resetsBiju Das
2025-02-03clk: renesas: r8a779h0: Add ISP core clocksNiklas Söderlund
2025-02-03clk: renesas: r8a779g0: Add ISP core clocksNiklas Söderlund
2025-02-03clk: renesas: r8a779a0: Add ISP core clocksNiklas Söderlund
2025-02-03clk: renesas: r8a779a0: Add FCPVX clocksNiklas Söderlund
2025-02-03clk: renesas: r9a07g044: Add clock and reset entry for DRP-AILad Prabhakar
2025-02-03clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ...Claudiu Beznea
2025-02-03clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validationLad Prabhakar
2025-01-07clk: renesas: r9a09g057: Add clock and reset entries for GICLad Prabhakar
2025-01-07clk: renesas: r9a09g057: Add reset entry for SYSLad Prabhakar
2025-01-07clk: renesas: r8a779g0: Add VSPX clocksJacopo Mondi
2025-01-07clk: renesas: r8a779g0: Add FCPVX clocksJacopo Mondi
2025-01-07clk: renesas: r9a09g047: Add I2C clocks/resetsBiju Das
2025-01-07clk: renesas: r9a09g047: Add CA55 core clocksBiju Das
2025-01-07clk: renesas: rzv2h: Add support for RZ/G3E SoCBiju Das
2025-01-07clk: renesas: rzv2h: Add MSTOP supportBiju Das
2024-12-10clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ...Claudiu Beznea
2024-12-10clk: renesas: r8a779h0: Add display clocksTomi Valkeinen
2024-12-10clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resetsLad Prabhakar
2024-12-10clk: renesas: rzv2h: Add selective Runtime PM support for clocksLad Prabhakar
2024-12-10clk: renesas: r9a06g032: Use BIT macro consistentlyWolfram Sang
2024-12-10clk: renesas: r9a06g032: Add restart handlerWolfram Sang
2024-12-03clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining ...Claudiu Beznea
2024-12-03clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSIClaudiu Beznea
2024-12-03clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()Javier Carrasco
2024-11-06clk: renesas: vbattb: Add VBATTB clock driverClaudiu Beznea
2024-11-03clk: renesas: rzg2l: Fix FOUTPOSTDIV clkBiju Das
2024-10-25clk: renesas: r9a08g045: Add power domain for RTCClaudiu Beznea
2024-10-25clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safeClaudiu Beznea
2024-10-25clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local onesClaudiu Beznea
generated by cgit (git 2.34.1) at 2025-08-05 01:59:09 +0000