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authorChanwoo Choi <cw00.choi@samsung.com>2015-02-03 09:13:50 +0900
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-02-05 19:30:34 +0100
commit6c5d76d15ab6da9b30af020a44e071eb5145e1a0 (patch)
treee7e02600bbedbdccaf7bd326786d90ac956801c0 /Documentation/devicetree/bindings/clock/exynos5433-clock.txt
parentdf40a13ca53e6f83ead88e718dd96654e75365ec (diff)
clk: samsung: exynos5433: Add clocks for CMU_ATLAS domain
This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which generates the clocks for Cortex-A57 Quad-core processsor, L2 cache controller and CoreSight. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/exynos5433-clock.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5433-clock.txt16
1 files changed, 16 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 0a7146861a27..7c1dccc4d72e 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -34,6 +34,9 @@ Required Properties:
which generates clocks for GSCALER IPs.
- "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
which generates clocks for Cortex-A53 Quad-core processor.
+ - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
+ which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
+ L2 cache controller.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -111,6 +114,10 @@ Required Properties:
- oscclk
- sclk_bus_pll_apollo
+ Input clocks for atlas clock controller:
+ - oscclk
+ - sclk_bus_pll_atlas
+
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
@@ -304,6 +311,15 @@ Example 2: Examples of clock controller nodes are listed below.
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
};
+ cmu_atlas: clock-controller@11800000 {
+ compatible = "samsung,exynos5433-cmu-atlas";
+ reg = <0x11800000 0x1088>;
+ #clock-cells = <1>;
+
+ clock-names = "oscclk", "sclk_bus_pll_atlas";
+ clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
+ };
+
Example 3: UART controller node that consumes the clock generated by the clock
controller.