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authorJoel Stanley <joel@jms.id.au>2018-05-30 15:47:40 +0930
committerOlof Johansson <olof@lixom.net>2018-06-02 01:18:53 -0700
commit927c2fc2db19fe6022be7c6dc0e380cb5c56a878 (patch)
tree387bb65347fd3c58cf79ef6388b12cca30280187 /arch/arm/boot/dts/aspeed-g4.dtsi
parent521ec1ca752d00c11f6c82fd40ae096e36bcf6db (diff)
ARM: dts: aspeed: Fix hwrng register address
The register address should be the full address of the rng, not the offset from the start of the SCU. Fixes: 5daa8212c08e ("ARM: dts: aspeed: Describe random number device") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g4.dtsi')
-rw-r--r--arch/arm/boot/dts/aspeed-g4.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 5e947ed496c2..75df1573380e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -145,9 +145,9 @@
};
- rng: hwrng@78 {
+ rng: hwrng@1e6e2078 {
compatible = "timeriomem_rng";
- reg = <0x78 0x4>;
+ reg = <0x1e6e2078 0x4>;
period = <1>;
quality = <100>;
};