diff options
| author | Sameer Pujar <spujar@nvidia.com> | 2023-06-29 10:42:17 +0530 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2023-07-13 17:13:25 +0200 |
| commit | dc6d5d85ed3a3fe566314f388bce4c71a26b1677 (patch) | |
| tree | c4e00412703a51bbd0050858b08f8008da306547 /arch/arm64/boot/dts/nvidia/tegra186.dtsi | |
| parent | e483fe34adab3197558b7284044c1b26f5ede20e (diff) | |
arm64: tegra: Update AHUB clock parent and rate
I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely that similar issues would be seen. Thus update the
AHUB clock parent and rates here as well for Tegra194, Tegra186
and Tegra210.
Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components")
Cc: stable@vger.kernel.org
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra186.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 7e4c496fd91c..2b3bb5d0af17 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -135,7 +135,8 @@ clocks = <&bpmp TEGRA186_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; + assigned-clock-rates = <81600000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x02900800 0x02900800 0x11800>; |