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authorOlof Johansson <olof@lixom.net>2019-06-25 04:31:37 -0700
committerOlof Johansson <olof@lixom.net>2019-06-25 04:31:37 -0700
commit750ee7858f5ae2894c0b12171fad3c8170c1e26c (patch)
tree8cb41634afe1193d63f324042ef34640eb73571f /arch/arm64/boot/dts/qcom/msm8996.dtsi
parent0914acd87fa089983f184785491d939a53f73e94 (diff)
parent2410fd450c09a126aefefc9106b4652285b5d60f (diff)
Merge tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 Updates for v5.3 * Switch to use second gen PON on PM8998 * Add PSCI cupidle states for MSM8996, MSM8998,and SDM845 * Add MSM8996 UFS phy reset controller * Add propre cpu capacity scaling on MSM8996 * Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996 * Enable SMMUs on MSM8996 * Add Dragonboard 845C * Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845 * Fixup CPU topology on SDM845 * Change USB1 to be peripheral on SDM845 MTP * Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998 * Update coresight bindings for MSM8916 * Update idle state names and entry-method on MSM8916 * Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states, and CDSP on QCS404 * Add reset-cells property to QCS404 GCC node * Fixup s3 max voltage, l3 min voltage, drive strength typo, and s3 supply definition on QCS404-evb * Fixup ADC outputs and VADC calibration on PMS405 * tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits) arm64: dts: qcom: qcs404-evb: fix vdd_apc supply arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon arm64: dts: qcom: msm8996: Enable SMMUs arm64: dts: qcom: msm8996: Correct apr-domain property arm64: dts: qcom: Add Dragonboard 845c arm64: dts: qcom: qcs404-evb: Enable PCIe arm64: dts: qcom: qcs404: Add PCIe related nodes arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes arm64: dts: qcom: msm8998: Add ANOC1 SMMU node arm64: dts: qcom: msm8996: Stop using legacy clock names arm64: dts: msm8996: fix PSCI entry-latency-us arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states arm64: dts: qcom: sdm845: Add Q6V5 MSS node arm64: dts: qcom: Add AOSS QMP node arm64: dts: qcom-qcs404: Add reset-cells to GCC node arm64: dts: qcom-msm8916: Update coresight DT bindings arm64: dts: qcom: msm8998: Add rpmpd node arm64: dts: qcom: qcs404: Add rpmpd node arm64: dts: qcom: qcs404: Move lpass and q6 into soc arm64: dts: qcom: qcs404: Fully describe the CDSP ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8996.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi59
1 files changed, 38 insertions, 21 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 942465d8aeb7..96c0a481f454 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -94,6 +94,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -106,6 +108,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
};
@@ -114,6 +118,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -126,6 +132,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
};
@@ -150,6 +158,19 @@
};
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "standalone-power-collapse";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <130>;
+ exit-latency-us = <80>;
+ min-residency-us = <300>;
+ };
+ };
};
thermal-zones {
@@ -846,10 +867,11 @@
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
+ resets = <&ufshc 0>;
status = "disabled";
};
- ufshc@624000 {
+ ufshc: ufshc@624000 {
compatible = "qcom,ufshc";
reg = <0x624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
@@ -905,6 +927,7 @@
<0 0>;
lanes-per-direction = <1>;
+ #reset-cells = <1>;
status = "disabled";
ufs_variant {
@@ -1154,7 +1177,6 @@
clock-names = "iface",
"bus";
#iommu-cells = <1>;
- status = "disabled";
};
camss: camss@a00000 {
@@ -1307,8 +1329,6 @@
clock-names = "iface", "bus";
power-domains = <&mmcc GPU_GDSC>;
-
- status = "disabled";
};
mdp_smmu: arm,smmu@d00000 {
@@ -1325,8 +1345,6 @@
clock-names = "iface", "bus";
power-domains = <&mmcc MDSS_GDSC>;
-
- status = "disabled";
};
lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
@@ -1353,7 +1371,6 @@
clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
<&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
clock-names = "iface", "bus";
- status = "disabled";
};
agnoc@0 {
@@ -1674,7 +1691,7 @@
#interrupt-cells = <1>;
clocks = <&mmcc MDSS_AHB_CLK>;
- clock-names = "iface_clk";
+ clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
@@ -1693,11 +1710,11 @@
<&mmcc MDSS_MDP_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
- clock-names = "iface_clk",
- "bus_clk",
- "core_clk",
- "iommu_clk",
- "vsync_clk";
+ clock-names = "iface",
+ "bus",
+ "core",
+ "iommu",
+ "vsync";
iommus = <&mdp_smmu 0>;
@@ -1732,11 +1749,11 @@
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names =
- "mdp_core_clk",
- "iface_clk",
- "core_clk",
- "alt_iface_clk",
- "extp_clk";
+ "mdp_core",
+ "iface",
+ "core",
+ "alt_iface",
+ "extp";
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
@@ -1773,8 +1790,8 @@
clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>;
- clock-names = "iface_clk",
- "ref_clk";
+ clock-names = "iface",
+ "ref";
};
};
};
@@ -1814,7 +1831,7 @@
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
- reg = <APR_DOMAIN_ADSP>;
+ qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;