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authorRex Zhu <Rex.Zhu@amd.com>2018-05-17 15:58:53 +0800
committerAlex Deucher <alexander.deucher@amd.com>2018-05-24 00:18:02 -0500
commitac06b4cfd78b79ec6c8306062801a4276a3e0c79 (patch)
treea2d062235d95335207ba8cdc05bade2e5375ebea /drivers/gpu/drm/amd/amdgpu/soc15_common.h
parent8dbb8cdf52dbc264d531d1e51f5e311bd1558c21 (diff)
drm/amdgpu: Add SOC15_WAIT_ON_RREG macro define
Add new macro to wait on a register field to be a specific value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15_common.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15_common.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index def865067edd..0942f492d2e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -47,6 +47,21 @@
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
+#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
+ do { \
+ uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+ uint32_t loop = adev->usec_timeout; \
+ while ((tmp_ & (mask)) != (expected_value)) { \
+ udelay(2); \
+ tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+ loop--; \
+ if (!loop) { \
+ ret = -ETIMEDOUT; \
+ break; \
+ } \
+ } \
+ } while (0)
+
#endif