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path: root/drivers/gpu/drm/amd/amdgpu/soc15_common.h
AgeCommit message (Expand)Author
2023-11-09drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2)Victor Lu
2023-11-09drm/amdgpu: add pcs xgmi v6.4.0 ras supportYang Wang
2023-11-09drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4)Victor Lu
2023-07-18drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)Victor Lu
2023-06-09drm/amdgpu: convert logical instance mask to physical oneTao Zhou
2023-06-09drm/amdgpu: fixes a JPEG get write/read pointer bugSonny Jiang
2023-06-09drm/amdgpu: add helpers to access registers on different AIDsLe Ma
2023-06-09drm/amdgpu: Use instance lookup table for GC 9.4.3Lijo Lazar
2023-06-09drm/amdgpu/: add more macro to support offset variantJames Zhu
2023-06-09drm/amdgpu: make the WREG32_SOC15_xx macro to support multi GCShiwu Zhang
2022-04-28drm/amdgpu: add new write field for soc21Stanley.Yang
2022-01-25drm/amdgpu: switch to amdgpu_sriov_rreg/wregHawking Zhang
2021-12-28drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitionsVictor Skvortsov
2021-07-23drm/amdgpu: Change the imprecise function nameRoy Sun
2021-06-07drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10Peng Ju Zhou
2021-06-04drm/amdgpu: soc15 register access through RLC should only apply to sriov runtimeshaoyunl
2021-05-21drm/amdgpu: Indirect register access for Navi12 sriovPeng Ju Zhou
2021-04-09drm/amdgpu: indirect register access for nv12 sriovPeng Ju Zhou
2021-03-23drm/amdgpu: enable watchdog feature for SQ of aldebaranDennis Li
2021-03-23drm/amdgpu: add ras support for gfx of aldebaranDennis Li
2020-07-01drm/amdgpu: fix unused variableJames Zhu
2020-04-24drm/amdgpu: provide RREG32_SOC15_NO_KIQ, will be used laterMonk Liu
2020-03-16drm/amdgpu: revise RLCG access pathMonk Liu
2019-11-26drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREGNathan Chancellor
2019-08-02drm/amdgpu: cleanup vega10 SRIOV code pathMonk Liu
2019-05-24drm/amdgpu: move the VCN DPG mode read and write to VCNLeo Liu
2019-05-24drm/amdgpu: add basic func for RLC program regTrigger Huang
2018-12-18drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREGJames Zhu
2018-09-26drm/amdgpu/soc15: fix warnings in register macroAlex Deucher
2018-09-26drm/amdgpu:Add DPG mode read/write macroJames Zhu
2018-09-13drm/amdgpu:Add error message when register failed to reach expected valueJames Zhu
2018-05-24drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu
2017-12-13drm/amdgpu: convert nbio to use callbacks (v2)Alex Deucher
2017-12-08drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offsetShaoyun Liu
2017-12-08drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const arrayShaoyun Liu
2017-12-08drm/amdgpu: Use dynamic IP offset for register access on SOC15Shaoyun Liu
2017-07-14drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro defineShaoyun Liu
2017-06-15drm/amd/amdgpu: Add offset variant to SOC15 macrosTom St Denis
2017-04-28drm/amd/amdgpu: Introduce new read/write macros for SOC15Tom St Denis
2017-03-29drm/amdgpu: add common soc15 headersKen Wang
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