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authorCharlene Liu <charlene.liu@amd.com>2019-05-07 15:12:02 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-06-22 09:34:10 -0500
commit4850ce697f9892df083bd7b3ec7c715404dd4279 (patch)
treec9022a6a03228f60403fd08c13a7d67dc8148356 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
parentfbc9ca671f4ffbc0c873de17cf2305ca438cb09e (diff)
drm/amd/display: Add hubp_init entry to hubp vtable
Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1 and DCN2. In addition, future HW will need to access the HUBPREQ_DEBUG and CUR_TTU_CNTL0 register for hubp_init. Add that here. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2ea72e965c1b..e7580e6e0fb6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -601,6 +601,8 @@ static void dcn20_init_hw(struct dc *dc)
hubp->power_gated = false;
pipe_ctx->stream_res.opp = NULL;
+ hubp->funcs->hubp_init(hubp);
+
//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
@@ -1224,7 +1226,7 @@ static void dcn20_program_all_pipe_in_tree(
dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
}
-static void dcn20_pipe_control_lock_global(
+void dcn20_pipe_control_lock_global(
struct dc *dc,
struct pipe_ctx *pipe,
bool lock)
@@ -1244,7 +1246,7 @@ static void dcn20_pipe_control_lock_global(
}
}
-static void dcn20_pipe_control_lock(
+void dcn20_pipe_control_lock(
struct dc *dc,
struct pipe_ctx *pipe,
bool lock)