diff options
| author | Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> | 2023-08-01 19:23:32 +0530 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2023-08-07 15:37:01 -0700 |
| commit | c224d89c8ee3a38fa9a974a33ad755e4709dbb41 (patch) | |
| tree | e8e4a218437016ca0ae3270c8e1ec5c83ee54fb6 /drivers/gpu/drm/i915/display/intel_cdclk.c | |
| parent | 927a8e383ab4d49fe40e1df8a92b22b62893d149 (diff) | |
drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines
Follow consistent naming convention. Replace BDW with
BROADWELL.
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-3-dnyaneshwar.bhadane@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cdclk.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index f18e1f8ef22e..f683802ce931 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3200,9 +3200,9 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) */ if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) dev_priv->display.cdclk.max_cdclk_freq = 450000; - else if (IS_BDW_ULX(dev_priv)) + else if (IS_BROADWELL_ULX(dev_priv)) dev_priv->display.cdclk.max_cdclk_freq = 450000; - else if (IS_BDW_ULT(dev_priv)) + else if (IS_BROADWELL_ULT(dev_priv)) dev_priv->display.cdclk.max_cdclk_freq = 540000; else dev_priv->display.cdclk.max_cdclk_freq = 675000; |