diff options
| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2019-11-20 07:55:49 -0600 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-12-23 14:06:15 +0100 |
| commit | 966b753cf3969553ca50bacd2b8c4ddade5ecc9e (patch) | |
| tree | 22f9c0d0de9450d6b6b2cecf5cb4a1b0b368a13d /drivers/iommu/amd_iommu_types.h | |
| parent | 813071438e83d338ba5cfe98b3b26c890dc0a6c0 (diff) | |
iommu/amd: Only support x2APIC with IVHD type 11h/40h
Current implementation for IOMMU x2APIC support makes use of
the MMIO access to MSI capability block registers, which requires
checking EFR[MsiCapMmioSup]. However, only IVHD type 11h/40h contain
the information, and not in the IVHD type 10h IOMMU feature reporting
field. Since the BIOS in newer systems, which supports x2APIC, would
normally contain IVHD type 11h/40h, remove the IOMMU_FEAT_XTSUP_SHIFT
check for IVHD type 10h, and only support x2APIC with IVHD type 11h/40h.
Fixes: 66929812955b ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/amd_iommu_types.h')
| -rw-r--r-- | drivers/iommu/amd_iommu_types.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index f8a7945f3df9..798e1533a147 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -377,7 +377,6 @@ #define IOMMU_CAP_EFR 27 /* IOMMU Feature Reporting Field (for IVHD type 10h */ -#define IOMMU_FEAT_XTSUP_SHIFT 0 #define IOMMU_FEAT_GASUP_SHIFT 6 /* IOMMU Extended Feature Register (EFR) */ |