diff options
| author | Rohan G Thomas <rohan.g.thomas@intel.com> | 2023-12-01 13:52:51 +0800 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2023-12-04 18:37:39 -0800 |
| commit | c3f3b97238f6fd87b9d90b9a995ee5e69f751a74 (patch) | |
| tree | e9dbb5099adf33f7cdc3920b49e0dc113f62dd95 /drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | |
| parent | 58f3240b3b93f880cae759ec2ff6ccfbf11903b7 (diff) | |
net: stmmac: Refactor EST implementation
Refactor EST implementation by moving common code for DWMAC4 and
DWXGMAC IPs into a separate EST module. EST implementation for DWMAC4
and DWXGMAC differs only for CSR base address, PTOV field offset
width, and PTOV clock multiplier value.
Thanks, Serge Semin and Jakub Kicinski for the suggestions on
refactoring EST implementation into a separate EST module.
Signed-off-by: Rohan G Thomas <rohan.g.thomas@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231201055252.1302-3-rohan.g.thomas@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 489f66094c49..207ff1799f2c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -284,49 +284,6 @@ #define XGMAC_TC_PRTY_MAP1 0x00001044 #define XGMAC_PSTC(x) GENMASK((x) * 8 + 7, (x) * 8) #define XGMAC_PSTC_SHIFT(x) ((x) * 8) -#define XGMAC_MTL_EST_CONTROL 0x00001050 -#define XGMAC_PTOV GENMASK(31, 23) -#define XGMAC_PTOV_SHIFT 23 -#define XGMAC_SSWL BIT(1) -#define XGMAC_EEST BIT(0) -#define XGMAC_MTL_EST_STATUS 0x00001058 -#define XGMAC_BTRL GENMASK(15, 8) -#define XGMAC_BTRL_SHIFT 8 -#define XGMAC_BTRL_MAX GENMASK(15, 8) -#define XGMAC_CGCE BIT(4) -#define XGMAC_HLBS BIT(3) -#define XGMAC_HLBF BIT(2) -#define XGMAC_BTRE BIT(1) -#define XGMAC_SWLC BIT(0) -#define XGMAC_MTL_EST_SCH_ERR 0x00001060 -#define XGMAC_MTL_EST_FRM_SZ_ERR 0x00001064 -#define XGMAC_MTL_EST_FRM_SZ_CAP 0x00001068 -#define XGMAC_SZ_CAP_HBFS_MASK GENMASK(14, 0) -#define XGMAC_SZ_CAP_HBFQ_SHIFT 16 -#define XGMAC_SZ_CAP_HBFQ_MASK(val) \ - ({ \ - typeof(val) _val = (val); \ - (_val > 4 ? GENMASK(18, 16) : \ - _val > 2 ? GENMASK(17, 16) : \ - BIT(16)); \ - }) -#define XGMAC_MTL_EST_INT_EN 0x00001070 -#define XGMAC_IECGCE BIT(4) -#define XGMAC_IEHS BIT(3) -#define XGMAC_IEHF BIT(2) -#define XGMAC_IEBE BIT(1) -#define XGMAC_IECC BIT(0) -#define XGMAC_MTL_EST_GCL_CONTROL 0x00001080 -#define XGMAC_BTR_LOW 0x0 -#define XGMAC_BTR_HIGH 0x1 -#define XGMAC_CTR_LOW 0x2 -#define XGMAC_CTR_HIGH 0x3 -#define XGMAC_TER 0x4 -#define XGMAC_LLR 0x5 -#define XGMAC_ADDR_SHIFT 8 -#define XGMAC_GCRR BIT(2) -#define XGMAC_SRWO BIT(0) -#define XGMAC_MTL_EST_GCL_DATA 0x00001084 #define XGMAC_MTL_RXP_CONTROL_STATUS 0x000010a0 #define XGMAC_RXPI BIT(31) #define XGMAC_NPE GENMASK(23, 16) |