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Diffstat (limited to 'Documentation/gpu/amdgpu/amdgpu-glossary.rst')
-rw-r--r-- | Documentation/gpu/amdgpu/amdgpu-glossary.rst | 120 |
1 files changed, 117 insertions, 3 deletions
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index 00a47ebb0b0f..30812d9d53c6 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -12,15 +12,39 @@ we have a dedicated glossary for Display Core at The number of CUs that are active on the system. The number of active CUs may be less than SE * SH * CU depending on the board configuration. + BACO + Bus Alive, Chip Off + + BOCO + Bus Off, Chip Off + + CE + Constant Engine + + CIK + Sea Islands + + CB + Color Buffer + CP Command Processor CPLIB Content Protection Library + CS + Command Submission + + CSB + Clear State Indirect Buffer + CU Compute Unit + DB + Depth Buffer + DFS Digital Frequency Synthesizer @@ -30,6 +54,9 @@ we have a dedicated glossary for Display Core at EOP End Of Pipe/Pipeline + FLR + Function Level Reset + GART Graphics Address Remapping Table. This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources @@ -42,6 +69,12 @@ we have a dedicated glossary for Display Core at GC Graphics and Compute + GDS + Global Data Share + + GE + Geometry Engine + GMC Graphic Memory Controller @@ -68,18 +101,33 @@ we have a dedicated glossary for Display Core at IB Indirect Buffer + IMU + Integrated Management Unit (Power Management support) + IP Intellectual Property blocks KCQ Kernel Compute Queue + KFD + Kernel Fusion Driver + KGQ Kernel Graphics Queue KIQ Kernel Interface Queue + MC + Memory Controller + + MCBP + Mid Command Buffer Preemption + + ME + MicroEngine (Graphics) + MEC MicroEngine Compute @@ -92,14 +140,29 @@ we have a dedicated glossary for Display Core at MQD Memory Queue Descriptor + PA + Primitive Assembler / Physical Address + + PFP + Pre-Fetch Parser (Graphics) + PPLib PowerPlay Library - PowerPlay is the power management component. PSP Platform Security Processor + RB + Render Backends. Some people called it ROPs. + RLC - RunList Controller + RunList Controller. This name is a remnant of past ages and doesn't have + much meaning today. It's a group of general-purpose helper engines for + the GFX block. It's involved in GFX power management and SR-IOV, among + other things. + + SC + Scan Converter SDMA System DMA @@ -107,17 +170,68 @@ we have a dedicated glossary for Display Core at SE Shader Engine + SGPR + Scalar General-Purpose Registers + SH SHader array - SMU - System Management Unit + SI + Southern Islands + + SMU/SMC + System Management Unit / System Management Controller + + SPI (AMDGPU) + Shader Processor Input + + SRLC + Save/Restore List Control + + SRLG + Save/Restore List GPM_MEM + + SRLS + Save/Restore List SRM_MEM SS Spread Spectrum + SX + Shader Export + + TA + Trusted Application + + TC + Texture Cache + + TOC + Table of Contents + + UMSCH + User Mode Scheduler + + UVD + Unified Video Decoder + VCE Video Compression Engine VCN Video Codec Next + + VGPR + Vector General-Purpose Registers + + VMID + Virtual Memory ID + + VPE + Video Processing Engine + + XCC + Accelerator Core Complex + + XCP + Accelerator Core Partition |