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-rw-r--r--arch/mips/alchemy/Kconfig12
-rw-r--r--arch/mips/alchemy/Makefile1
-rw-r--r--arch/mips/alchemy/Platform3
-rw-r--r--arch/mips/alchemy/board-gpr.c32
-rw-r--r--arch/mips/alchemy/board-mtx1.c213
-rw-r--r--arch/mips/alchemy/board-xxs1500.c34
-rw-r--r--arch/mips/alchemy/common/Makefile1
-rw-r--r--arch/mips/alchemy/common/clock.c34
-rw-r--r--arch/mips/alchemy/common/dbdma.c41
-rw-r--r--arch/mips/alchemy/common/dma.c23
-rw-r--r--arch/mips/alchemy/common/gpiolib.c16
-rw-r--r--arch/mips/alchemy/common/irq.c24
-rw-r--r--arch/mips/alchemy/common/platform.c40
-rw-r--r--arch/mips/alchemy/common/prom.c26
-rw-r--r--arch/mips/alchemy/common/setup.c54
-rw-r--r--arch/mips/alchemy/common/sleeper.S6
-rw-r--r--arch/mips/alchemy/common/time.c25
-rw-r--r--arch/mips/alchemy/common/usb.c13
-rw-r--r--arch/mips/alchemy/common/vss.c1
-rw-r--r--arch/mips/alchemy/devboards/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c1
-rw-r--r--arch/mips/alchemy/devboards/db1000.c102
-rw-r--r--arch/mips/alchemy/devboards/db1200.c44
-rw-r--r--arch/mips/alchemy/devboards/db1300.c30
-rw-r--r--arch/mips/alchemy/devboards/db1550.c5
-rw-r--r--arch/mips/alchemy/devboards/platform.c17
-rw-r--r--arch/mips/alchemy/devboards/pm.c2
27 files changed, 378 insertions, 423 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 83b288b95b16..6ca81e1bd35c 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,12 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-# au1000-style gpio and interrupt controllers
-config ALCHEMY_GPIOINT_AU1000
- bool
-
-# au1300-style GPIO/INT controller
-config ALCHEMY_GPIOINT_AU1300
- bool
-
choice
prompt "Machine type"
depends on MIPS_ALCHEMY
@@ -15,7 +7,6 @@ choice
config MIPS_MTX1
bool "4G Systems MTX-1 board"
select HAVE_PCI
- select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
@@ -23,6 +14,7 @@ config MIPS_DB1XXX
bool "Alchemy DB1XXX / PB1XXX boards"
select GPIOLIB
select HAVE_PCI
+ select HAVE_PATA_PLATFORM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
help
@@ -33,13 +25,11 @@ config MIPS_DB1XXX
config MIPS_XXS1500
bool "MyCable XXS1500 board"
- select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_GPR
bool "Trapeze ITS GPR board"
- select ALCHEMY_GPIOINT_AU1000
select HAVE_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/alchemy/Makefile b/arch/mips/alchemy/Makefile
index aac3b179bbc0..fabbc7019065 100644
--- a/arch/mips/alchemy/Makefile
+++ b/arch/mips/alchemy/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MIPS_GPR) += board-gpr.o
obj-$(CONFIG_MIPS_MTX1) += board-mtx1.o
obj-$(CONFIG_MIPS_XXS1500) += board-xxs1500.o
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 33c9da3b077b..c8cff50b0eda 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -15,19 +15,16 @@ load-$(CONFIG_MIPS_DB1XXX) += 0xffffffff80100000
#
# 4G-Systems MTX-1 "MeshCube" wireless router
#
-platform-$(CONFIG_MIPS_MTX1) += alchemy/
load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
#
# MyCable eval board
#
-platform-$(CONFIG_MIPS_XXS1500) += alchemy/
load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
#
# Trapeze ITS GRP board
#
-platform-$(CONFIG_MIPS_GPR) += alchemy/
load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
# boards can specify their own <gpio.h> in one of their include dirs.
diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index ddff9a02513d..f587c40b6d00 100644
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -1,21 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GPR board platform device registration (Au1550)
*
* Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/delay.h>
@@ -44,23 +31,6 @@ const char *get_system_type(void)
return "GPR";
}
-void __init prom_init(void)
-{
- unsigned char *memsize_str;
- unsigned long memsize;
-
- prom_argc = fw_arg0;
- prom_argv = (char **)fw_arg1;
- prom_envp = (char **)fw_arg2;
-
- prom_init_cmdline();
-
- memsize_str = prom_getenv("memsize");
- if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
- memsize = 0x04000000;
- add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 9d9d4ee31605..cb6be58808a0 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -1,31 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MTX-1 platform devices registration (Au1500)
*
* Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
#include <linux/gpio/machine.h>
-#include <linux/gpio_keys.h>
+#include <linux/gpio/property.h>
#include <linux/input.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
@@ -43,23 +28,6 @@ const char *get_system_type(void)
return "MTX-1";
}
-void __init prom_init(void)
-{
- unsigned char *memsize_str;
- unsigned long memsize;
-
- prom_argc = fw_arg0;
- prom_argv = (char **)fw_arg1;
- prom_envp = (char **)fw_arg2;
-
- prom_init_cmdline();
-
- memsize_str = prom_getenv("memsize");
- if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
- memsize = 0x04000000;
- add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
@@ -110,64 +78,134 @@ void __init board_setup(void)
/******************************************************************************/
-static struct gpio_keys_button mtx1_gpio_button[] = {
- {
- .gpio = 207,
- .code = BTN_0,
- .desc = "System button",
- }
+static const struct software_node mtx1_gpiochip_node = {
+ .name = "alchemy-gpio2",
};
-static struct gpio_keys_platform_data mtx1_buttons_data = {
- .buttons = mtx1_gpio_button,
- .nbuttons = ARRAY_SIZE(mtx1_gpio_button),
+static const struct software_node mtx1_gpio_keys_node = {
+ .name = "mtx1-gpio-keys",
};
-static struct platform_device mtx1_button = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &mtx1_buttons_data,
- }
+static const struct property_entry mtx1_button_props[] = {
+ PROPERTY_ENTRY_U32("linux,code", BTN_0),
+ PROPERTY_ENTRY_GPIO("gpios", &mtx1_gpiochip_node, 7, GPIO_ACTIVE_HIGH),
+ PROPERTY_ENTRY_STRING("label", "System button"),
+ { }
};
-static struct gpiod_lookup_table mtx1_wdt_gpio_table = {
- .dev_id = "mtx1-wdt.0",
- .table = {
- /* Global number 215 is offset 15 on Alchemy GPIO 2 */
- GPIO_LOOKUP("alchemy-gpio2", 15, NULL, GPIO_ACTIVE_HIGH),
- { },
- },
+static const struct software_node mtx1_button_node = {
+ .parent = &mtx1_gpio_keys_node,
+ .properties = mtx1_button_props,
+};
+
+static const struct software_node *mtx1_gpio_keys_swnodes[] __initconst = {
+ &mtx1_gpio_keys_node,
+ &mtx1_button_node,
+ NULL
+};
+
+static void __init mtx1_keys_init(void)
+{
+ struct platform_device_info keys_info = {
+ .name = "gpio-keys",
+ .id = PLATFORM_DEVID_NONE,
+ };
+ struct platform_device *pd;
+ int err;
+
+ err = software_node_register_node_group(mtx1_gpio_keys_swnodes);
+ if (err) {
+ pr_err("failed to register gpio-keys software nodes: %d\n", err);
+ return;
+ }
+
+ keys_info.fwnode = software_node_fwnode(&mtx1_gpio_keys_node);
+
+ pd = platform_device_register_full(&keys_info);
+ err = PTR_ERR_OR_ZERO(pd);
+ if (err)
+ pr_err("failed to create gpio-keys device: %d\n", err);
+}
+
+/* Global number 215 is offset 15 on Alchemy GPIO 2 */
+static const struct property_entry mtx1_wdt_props[] = {
+ PROPERTY_ENTRY_GPIO("gpios", &mtx1_gpiochip_node, 15, GPIO_ACTIVE_HIGH),
+ { }
};
-static struct platform_device mtx1_wdt = {
+static struct platform_device_info mtx1_wdt_info __initconst = {
.name = "mtx1-wdt",
.id = 0,
+ .properties = mtx1_wdt_props,
};
-static const struct gpio_led default_leds[] = {
- {
- .name = "mtx1:green",
- .gpio = 211,
- }, {
- .name = "mtx1:red",
- .gpio = 212,
- },
+static void __init mtx1_wdt_init(void)
+{
+ struct platform_device *pd;
+ int err;
+
+ pd = platform_device_register_full(&mtx1_wdt_info);
+ err = PTR_ERR_OR_ZERO(pd);
+ if (err)
+ pr_err("failed to create gpio-keys device: %d\n", err);
+}
+
+static const struct software_node mtx1_gpio_leds_node = {
+ .name = "mtx1-leds",
};
-static struct gpio_led_platform_data mtx1_led_data = {
- .num_leds = ARRAY_SIZE(default_leds),
- .leds = default_leds,
+static const struct property_entry mtx1_green_led_props[] = {
+ PROPERTY_ENTRY_GPIO("gpios", &mtx1_gpiochip_node, 11, GPIO_ACTIVE_HIGH),
+ { }
};
-static struct platform_device mtx1_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mtx1_led_data,
- }
+static const struct software_node mtx1_green_led_node = {
+ .name = "mtx1:green",
+ .parent = &mtx1_gpio_leds_node,
+ .properties = mtx1_green_led_props,
+};
+
+static const struct property_entry mtx1_red_led_props[] = {
+ PROPERTY_ENTRY_GPIO("gpios", &mtx1_gpiochip_node, 12, GPIO_ACTIVE_HIGH),
+ { }
};
+static const struct software_node mtx1_red_led_node = {
+ .name = "mtx1:red",
+ .parent = &mtx1_gpio_leds_node,
+ .properties = mtx1_red_led_props,
+};
+
+static const struct software_node *mtx1_gpio_leds_swnodes[] = {
+ &mtx1_gpio_leds_node,
+ &mtx1_green_led_node,
+ &mtx1_red_led_node,
+ NULL
+};
+
+static void __init mtx1_leds_init(void)
+{
+ struct platform_device_info led_info = {
+ .name = "leds-gpio",
+ .id = PLATFORM_DEVID_NONE,
+ };
+ struct platform_device *led_dev;
+ int err;
+
+ err = software_node_register_node_group(mtx1_gpio_leds_swnodes);
+ if (err) {
+ pr_err("failed to register LED software nodes: %d\n", err);
+ return;
+ }
+
+ led_info.fwnode = software_node_fwnode(&mtx1_gpio_leds_node);
+
+ led_dev = platform_device_register_full(&led_info);
+ err = PTR_ERR_OR_ZERO(led_dev);
+ if (err)
+ pr_err("failed to create LED device: %d\n", err);
+}
+
static struct mtd_partition mtx1_mtd_partitions[] = {
{
.name = "filesystem",
@@ -277,9 +315,6 @@ static struct platform_device mtx1_pci_host = {
static struct platform_device *mtx1_devs[] __initdata = {
&mtx1_pci_host,
- &mtx1_gpio_leds,
- &mtx1_wdt,
- &mtx1_button,
&mtx1_mtd,
};
@@ -300,16 +335,18 @@ static int __init mtx1_register_devices(void)
au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
- rc = gpio_request(mtx1_gpio_button[0].gpio,
- mtx1_gpio_button[0].desc);
- if (rc < 0) {
- printk(KERN_INFO "mtx1: failed to request %d\n",
- mtx1_gpio_button[0].gpio);
- goto out;
- }
- gpio_direction_input(mtx1_gpio_button[0].gpio);
-out:
- gpiod_add_lookup_table(&mtx1_wdt_gpio_table);
- return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
+ rc = software_node_register(&mtx1_gpiochip_node);
+ if (rc)
+ return rc;
+
+ rc = platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
+ if (rc)
+ return rc;
+
+ mtx1_leds_init();
+ mtx1_wdt_init();
+ mtx1_keys_init();
+
+ return 0;
}
arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c
index 5f05b8714385..f175bce2987f 100644
--- a/arch/mips/alchemy/board-xxs1500.c
+++ b/arch/mips/alchemy/board-xxs1500.c
@@ -1,23 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* BRIEF MODULE DESCRIPTION
* MyCable XXS1500 board support
*
* Copyright 2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
@@ -31,6 +18,7 @@
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/gpio-au1000.h>
#include <prom.h>
const char *get_system_type(void)
@@ -38,24 +26,6 @@ const char *get_system_type(void)
return "XXS1500";
}
-void __init prom_init(void)
-{
- unsigned char *memsize_str;
- unsigned long memsize;
-
- prom_argc = fw_arg0;
- prom_argv = (char **)fw_arg1;
- prom_envp = (char **)fw_arg2;
-
- prom_init_cmdline();
-
- memsize_str = prom_getenv("memsize");
- if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
- memsize = 0x04000000;
-
- add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 23800b8e67e5..a0e94388dcf7 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright 2000, 2008 MontaVista Software Inc.
# Author: MontaVista Software, Inc. <source@mvista.com>
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index d129475fd40d..551b0d21d9dc 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -111,7 +111,7 @@ static struct clk_aliastable {
/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
static spinlock_t alchemy_clk_fg0_lock;
static spinlock_t alchemy_clk_fg1_lock;
-static spinlock_t alchemy_clk_csrc_lock;
+static DEFINE_SPINLOCK(alchemy_clk_csrc_lock);
/* CPU Core clock *****************************************************/
@@ -152,6 +152,7 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
{
struct clk_init_data id;
struct clk_hw *h;
+ struct clk *clk;
h = kzalloc(sizeof(*h), GFP_KERNEL);
if (!h)
@@ -160,11 +161,17 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
id.name = ALCHEMY_CPU_CLK;
id.parent_names = &parent_name;
id.num_parents = 1;
- id.flags = CLK_IS_BASIC;
+ id.flags = 0;
id.ops = &alchemy_clkops_cpu;
h->init = &id;
- return clk_register(NULL, h);
+ clk = clk_register(NULL, h);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register clock\n");
+ kfree(h);
+ }
+
+ return clk;
}
/* AUXPLLs ************************************************************/
@@ -204,30 +211,34 @@ static int alchemy_clk_aux_setr(struct clk_hw *hw,
return 0;
}
-static long alchemy_clk_aux_roundr(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static int alchemy_clk_aux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
unsigned long mult;
- if (!rate || !*parent_rate)
+ if (!req->rate || !req->best_parent_rate) {
+ req->rate = 0;
+
return 0;
+ }
- mult = rate / (*parent_rate);
+ mult = req->rate / req->best_parent_rate;
if (mult && (mult < 7))
mult = 7;
if (mult > a->maxmult)
mult = a->maxmult;
- return (*parent_rate) * mult;
+ req->rate = req->best_parent_rate * mult;
+
+ return 0;
}
static const struct clk_ops alchemy_clkops_aux = {
.recalc_rate = alchemy_clk_aux_recalc,
.set_rate = alchemy_clk_aux_setr,
- .round_rate = alchemy_clk_aux_roundr,
+ .determine_rate = alchemy_clk_aux_determine_rate,
};
static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
@@ -764,7 +775,7 @@ static int __init alchemy_clk_init_fgens(int ctype)
}
id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
- a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
+ a = kcalloc(6, sizeof(*a), GFP_KERNEL);
if (!a)
return -ENOMEM;
@@ -989,7 +1000,6 @@ static int __init alchemy_clk_setup_imux(int ctype)
if (!a)
return -ENOMEM;
- spin_lock_init(&alchemy_clk_csrc_lock);
ret = 0;
for (i = 0; i < 6; i++) {
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 4ca2c28878e0..6c2c2010bbae 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -30,6 +30,7 @@
*
*/
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -574,7 +575,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
dp++;
}
- /* Make last descrptor point to the first. */
+ /* Make last descriptor point to the first. */
dp--;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
@@ -623,17 +624,18 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
/*
- * There is an errata on the Au1200/Au1550 parts that could result
- * in "stale" data being DMA'ed. It has to do with the snoop logic on
- * the cache eviction buffer. DMA_NONCOHERENT is on by default for
- * these parts. If it is fixed in the future, these dma_cache_inv will
- * just be nothing more than empty macros. See io.h.
+ * There is an erratum on certain Au1200/Au1550 revisions that could
+ * result in "stale" data being DMA'ed. It has to do with the snoop
+ * logic on the cache eviction buffer. dma_default_coherent is set
+ * to false on these parts.
*/
- dma_cache_wback_inv((unsigned long)buf, nbytes);
+ if (!dma_default_coherent)
+ dma_cache_wback_inv(KSEG0ADDR(buf), nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
wmb(); /* drain writebuffer */
dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
ctp->chan_ptr->ddma_dbell = 0;
+ wmb(); /* force doorbell write out to dma engine */
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
@@ -685,17 +687,18 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
#endif
/*
- * There is an errata on the Au1200/Au1550 parts that could result in
- * "stale" data being DMA'ed. It has to do with the snoop logic on the
- * cache eviction buffer. DMA_NONCOHERENT is on by default for these
- * parts. If it is fixed in the future, these dma_cache_inv will just
- * be nothing more than empty macros. See io.h.
+ * There is an erratum on certain Au1200/Au1550 revisions that could
+ * result in "stale" data being DMA'ed. It has to do with the snoop
+ * logic on the cache eviction buffer. dma_default_coherent is set
+ * to false on these parts.
*/
- dma_cache_inv((unsigned long)buf, nbytes);
+ if (!dma_default_coherent)
+ dma_cache_inv(KSEG0ADDR(buf), nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
wmb(); /* drain writebuffer */
dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
ctp->chan_ptr->ddma_dbell = 0;
+ wmb(); /* force doorbell write out to dma engine */
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
@@ -979,7 +982,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
-static int alchemy_dbdma_suspend(void)
+static int alchemy_dbdma_suspend(void *data)
{
int i;
void __iomem *addr;
@@ -1016,7 +1019,7 @@ static int alchemy_dbdma_suspend(void)
return 0;
}
-static void alchemy_dbdma_resume(void)
+static void alchemy_dbdma_resume(void *data)
{
int i;
void __iomem *addr;
@@ -1041,11 +1044,15 @@ static void alchemy_dbdma_resume(void)
}
}
-static struct syscore_ops alchemy_dbdma_syscore_ops = {
+static const struct syscore_ops alchemy_dbdma_syscore_ops = {
.suspend = alchemy_dbdma_suspend,
.resume = alchemy_dbdma_resume,
};
+static struct syscore alchemy_dbdma_syscore = {
+ .ops = &alchemy_dbdma_syscore_ops,
+};
+
static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
{
int ret;
@@ -1068,7 +1075,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
else {
dbdma_initialized = 1;
- register_syscore_ops(&alchemy_dbdma_syscore_ops);
+ register_syscore(&alchemy_dbdma_syscore);
}
return ret;
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 973049b5bd61..44d8433b1f45 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -131,29 +131,6 @@ static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
{ AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */
};
-void dump_au1000_dma_channel(unsigned int dmanr)
-{
- struct dma_chan *chan;
-
- if (dmanr >= NUM_AU1000_DMA_CHANNELS)
- return;
- chan = &au1000_dma_table[dmanr];
-
- printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
- printk(KERN_INFO " mode = 0x%08x\n",
- __raw_readl(chan->io + DMA_MODE_SET));
- printk(KERN_INFO " addr = 0x%08x\n",
- __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
- printk(KERN_INFO " start0 = 0x%08x\n",
- __raw_readl(chan->io + DMA_BUFFER0_START));
- printk(KERN_INFO " start1 = 0x%08x\n",
- __raw_readl(chan->io + DMA_BUFFER1_START));
- printk(KERN_INFO " count0 = 0x%08x\n",
- __raw_readl(chan->io + DMA_BUFFER0_COUNT));
- printk(KERN_INFO " count1 = 0x%08x\n",
- __raw_readl(chan->io + DMA_BUFFER1_COUNT));
-}
-
/*
* Finds a free channel, and binds the requested device to it.
* Returns the allocated channel number, or negative on error.
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 7d5da5edd74d..e79e26ffac99 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -23,8 +23,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Notes :
- * This file must ONLY be built when CONFIG_GPIOLIB=y and
- * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
* au1000 SoC have only one GPIO block : GPIO1
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
* Au1300 is totally different: 1 block with up to 128 GPIOs
@@ -33,7 +31,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
-#include <linux/gpio.h>
+#include <linux/gpio/driver.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/gpio-au1300.h>
@@ -42,9 +40,11 @@ static int gpio2_get(struct gpio_chip *chip, unsigned offset)
return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
}
-static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
+static int gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
{
alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
+
+ return 0;
}
static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -70,10 +70,12 @@ static int gpio1_get(struct gpio_chip *chip, unsigned offset)
return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
}
-static void gpio1_set(struct gpio_chip *chip,
+static int gpio1_set(struct gpio_chip *chip,
unsigned offset, int value)
{
alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
+
+ return 0;
}
static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -121,9 +123,11 @@ static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE);
}
-static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
+static int alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
{
au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
+
+ return 0;
}
static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index da9f9220048f..2403afcd2fb9 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -758,7 +758,7 @@ static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
wmb();
}
-static int alchemy_ic_suspend(void)
+static int alchemy_ic_suspend(void *data)
{
alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
alchemy_gpic_pmdata);
@@ -767,7 +767,7 @@ static int alchemy_ic_suspend(void)
return 0;
}
-static void alchemy_ic_resume(void)
+static void alchemy_ic_resume(void *data)
{
alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
&alchemy_gpic_pmdata[7]);
@@ -775,7 +775,7 @@ static void alchemy_ic_resume(void)
alchemy_gpic_pmdata);
}
-static int alchemy_gpic_suspend(void)
+static int alchemy_gpic_suspend(void *data)
{
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
int i;
@@ -806,7 +806,7 @@ static int alchemy_gpic_suspend(void)
return 0;
}
-static void alchemy_gpic_resume(void)
+static void alchemy_gpic_resume(void *data)
{
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
int i;
@@ -837,16 +837,24 @@ static void alchemy_gpic_resume(void)
wmb();
}
-static struct syscore_ops alchemy_ic_pmops = {
+static const struct syscore_ops alchemy_ic_pmops = {
.suspend = alchemy_ic_suspend,
.resume = alchemy_ic_resume,
};
-static struct syscore_ops alchemy_gpic_pmops = {
+static struct syscore alchemy_ic_pm = {
+ .ops = &alchemy_ic_pmops,
+};
+
+static const struct syscore_ops alchemy_gpic_pmops = {
.suspend = alchemy_gpic_suspend,
.resume = alchemy_gpic_resume,
};
+static struct syscore alchemy_gpic_pm = {
+ .ops = &alchemy_gpic_pmops,
+};
+
/******************************************************************************/
/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
@@ -880,7 +888,7 @@ static void __init au1000_init_irq(struct alchemy_irqmap *map)
ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
- register_syscore_ops(&alchemy_ic_pmops);
+ register_syscore(&alchemy_ic_pm);
mips_cpu_irq_init();
/* register all 64 possible IC0+IC1 irq sources as type "none".
@@ -925,7 +933,7 @@ static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints)
int i;
void __iomem *bank_base;
- register_syscore_ops(&alchemy_gpic_pmops);
+ register_syscore(&alchemy_gpic_pm);
mips_cpu_irq_init();
/* disable & ack all possible interrupt sources */
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 1454d9f6ab2d..da74cae6b43a 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -51,9 +51,9 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
#define PORT(_base, _irq) \
{ \
.mapbase = _base, \
+ .mapsize = 0x1000, \
.irq = _irq, \
.regshift = 2, \
- .iotype = UPIO_AU, \
.flags = UPF_SKIP_TEST | UPF_IOREMAP | \
UPF_FIXED_TYPE, \
.type = PORT_16550A, \
@@ -124,16 +124,20 @@ static void __init alchemy_setup_uarts(int ctype)
au1xx0_uart_device.dev.platform_data = ports;
/* Fill up uartclk. */
- for (s = 0; s < c; s++)
+ for (s = 0; s < c; s++) {
ports[s].uartclk = uartclk;
+ if (au_platform_setup(&ports[s]) < 0) {
+ kfree(ports);
+ printk(KERN_INFO "Alchemy: missing support for UARTs\n");
+ return;
+ }
+ }
if (platform_device_register(&au1xx0_uart_device))
printk(KERN_INFO "Alchemy: failed to register UARTs\n");
}
-/* The dmamask must be set for OHCI/EHCI to work */
-static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
-static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
+static u64 alchemy_all_dmamask = DMA_BIT_MASK(32);
/* Power on callback for the ehci platform driver */
static int alchemy_ehci_power_on(struct platform_device *pdev)
@@ -231,7 +235,7 @@ static void __init alchemy_setup_usb(int ctype)
res[1].flags = IORESOURCE_IRQ;
pdev->name = "ohci-platform";
pdev->id = 0;
- pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+ pdev->dev.dma_mask = &alchemy_all_dmamask;
pdev->dev.platform_data = &alchemy_ohci_pdata;
if (platform_device_register(pdev))
@@ -251,7 +255,7 @@ static void __init alchemy_setup_usb(int ctype)
res[1].flags = IORESOURCE_IRQ;
pdev->name = "ehci-platform";
pdev->id = 0;
- pdev->dev.dma_mask = &alchemy_ehci_dmamask;
+ pdev->dev.dma_mask = &alchemy_all_dmamask;
pdev->dev.platform_data = &alchemy_ehci_pdata;
if (platform_device_register(pdev))
@@ -271,7 +275,7 @@ static void __init alchemy_setup_usb(int ctype)
res[1].flags = IORESOURCE_IRQ;
pdev->name = "ohci-platform";
pdev->id = 1;
- pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+ pdev->dev.dma_mask = &alchemy_all_dmamask;
pdev->dev.platform_data = &alchemy_ohci_pdata;
if (platform_device_register(pdev))
@@ -338,7 +342,11 @@ static struct platform_device au1xxx_eth0_device = {
.name = "au1000-eth",
.id = 0,
.num_resources = MAC_RES_COUNT,
- .dev.platform_data = &au1xxx_eth0_platform_data,
+ .dev = {
+ .dma_mask = &alchemy_all_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &au1xxx_eth0_platform_data,
+ },
};
static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
@@ -370,7 +378,11 @@ static struct platform_device au1xxx_eth1_device = {
.name = "au1000-eth",
.id = 1,
.num_resources = MAC_RES_COUNT,
- .dev.platform_data = &au1xxx_eth1_platform_data,
+ .dev = {
+ .dma_mask = &alchemy_all_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &au1xxx_eth1_platform_data,
+ },
};
void __init au1xxx_override_eth_cfg(unsigned int port,
@@ -397,8 +409,8 @@ static void __init alchemy_setup_macs(int ctype)
if (alchemy_get_macs(ctype) < 1)
return;
- macres = kmemdup(au1xxx_eth0_resources[ctype],
- sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
+ macres = kmemdup_array(au1xxx_eth0_resources[ctype], MAC_RES_COUNT,
+ sizeof(*macres), GFP_KERNEL);
if (!macres) {
printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
return;
@@ -418,8 +430,8 @@ static void __init alchemy_setup_macs(int ctype)
if (alchemy_get_macs(ctype) < 2)
return;
- macres = kmemdup(au1xxx_eth1_resources[ctype],
- sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
+ macres = kmemdup_array(au1xxx_eth1_resources[ctype], MAC_RES_COUNT,
+ sizeof(*macres), GFP_KERNEL);
if (!macres) {
printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
return;
diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c
index af312b5e33f6..20d30f6265cd 100644
--- a/arch/mips/alchemy/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
@@ -34,9 +34,13 @@
*/
#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/memblock.h>
+#include <linux/sizes.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
+#include <prom.h>
int prom_argc;
char **prom_argv;
@@ -76,6 +80,24 @@ char *prom_getenv(char *envname)
return NULL;
}
+void __init prom_init(void)
+{
+ unsigned char *memsize_str;
+ unsigned long memsize;
+
+ prom_argc = (int)fw_arg0;
+ prom_argv = (char **)fw_arg1;
+ prom_envp = (char **)fw_arg2;
+
+ prom_init_cmdline();
+
+ memsize_str = prom_getenv("memsize");
+ if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
+ memsize = SZ_64M; /* minimum memsize is 64MB RAM */
+
+ memblock_add(0, memsize);
+}
+
static inline unsigned char str2hexnum(unsigned char c)
{
if (c >= '0' && c <= '9')
@@ -122,7 +144,3 @@ int __init prom_get_ethernet_addr(char *ethernet_addr)
return 0;
}
-
-void __init prom_free_prom_memory(void)
-{
-}
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 7faaa6d593a7..c35b4f809d51 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -27,14 +27,30 @@
#include <linux/init.h>
#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
-#include <asm/dma-coherence.h>
+#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <au1000.h>
-extern void __init board_setup(void);
-extern void __init alchemy_set_lpj(void);
+static bool alchemy_dma_coherent(void)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ return false;
+ case ALCHEMY_CPU_AU1200:
+ /* Au1200 AB USB does not support coherent memory */
+ if ((read_c0_prid() & PRID_REV_MASK) == 0)
+ return false;
+ return true;
+ default:
+ return true;
+ }
+}
void __init plat_mem_setup(void)
{
@@ -47,20 +63,7 @@ void __init plat_mem_setup(void)
/* Clear to obtain best system bus performance */
clear_c0_config(1 << 19); /* Clear Config[OD] */
- hw_coherentio = 0;
- coherentio = IO_COHERENCE_ENABLED;
- switch (alchemy_get_cputype()) {
- case ALCHEMY_CPU_AU1000:
- case ALCHEMY_CPU_AU1500:
- case ALCHEMY_CPU_AU1100:
- coherentio = IO_COHERENCE_DISABLED;
- break;
- case ALCHEMY_CPU_AU1200:
- /* Au1200 AB USB does not support coherent memory */
- if (0 == (read_c0_prid() & PRID_REV_MASK))
- coherentio = IO_COHERENCE_DISABLED;
- break;
- }
+ dma_default_coherent = alchemy_dma_coherent();
board_setup(); /* board specific setup */
@@ -72,9 +75,9 @@ void __init plat_mem_setup(void)
iomem_resource.end = IOMEM_RESOURCE_END;
}
-#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
+#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
/* This routine should be valid for all Au1x based boards */
-phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
+phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
unsigned long start = ALCHEMY_PCI_MEMWIN_START;
unsigned long end = ALCHEMY_PCI_MEMWIN_END;
@@ -90,5 +93,14 @@ phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
/* default nop */
return phys_addr;
}
-EXPORT_SYMBOL(__fixup_bigphys_addr);
-#endif
+
+static inline unsigned long io_remap_pfn_range_pfn(unsigned long pfn,
+ unsigned long size)
+{
+ phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
+
+ return phys_addr >> PAGE_SHIFT;
+}
+EXPORT_SYMBOL(io_remap_pfn_range_pfn);
+
+#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index c73d81270b42..13586d224314 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -1,13 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2002 Embedded Edge, LLC
* Author: dan@embeddededge.com
*
* Sleep helper for Au1xxx sleep mode.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#include <asm/asm.h>
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 166e842c044f..d794ffb67412 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
*
@@ -10,19 +11,6 @@
*
* ########################################################################
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* ########################################################################
*
* Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
@@ -84,13 +72,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
.cpumask = cpu_possible_mask,
};
-static struct irqaction au1x_rtcmatch2_irqaction = {
- .handler = au1x_rtcmatch2_irq,
- .flags = IRQF_TIMER,
- .name = "timer",
- .dev_id = &au1x_rtcmatch2_clockdev,
-};
-
static int __init alchemy_time_init(unsigned int m2int)
{
struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
@@ -142,7 +123,9 @@ static int __init alchemy_time_init(unsigned int m2int)
cd->min_delta_ns = clockevent_delta2ns(9, cd);
cd->min_delta_ticks = 9; /* ~0.28ms */
clockevents_register_device(cd);
- setup_irq(m2int, &au1x_rtcmatch2_irqaction);
+ if (request_irq(m2int, au1x_rtcmatch2_irq, IRQF_TIMER, "timer",
+ &au1x_rtcmatch2_clockdev))
+ pr_err("Failed to register timer interrupt\n");
printk(KERN_INFO "Alchemy clocksource installed\n");
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
index 634edd3ded38..a55f32bf517c 100644
--- a/arch/mips/alchemy/common/usb.c
+++ b/arch/mips/alchemy/common/usb.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* USB block power/access management abstraction.
*
@@ -579,22 +580,26 @@ static void alchemy_usb_pm(int susp)
}
}
-static int alchemy_usb_suspend(void)
+static int alchemy_usb_suspend(void *data)
{
alchemy_usb_pm(1);
return 0;
}
-static void alchemy_usb_resume(void)
+static void alchemy_usb_resume(void *data)
{
alchemy_usb_pm(0);
}
-static struct syscore_ops alchemy_usb_pm_ops = {
+static const struct syscore_ops alchemy_usb_pm_syscore_ops = {
.suspend = alchemy_usb_suspend,
.resume = alchemy_usb_resume,
};
+static struct syscore alchemy_usb_pm_syscore = {
+ .ops = &alchemy_usb_pm_syscore_ops,
+};
+
static int __init alchemy_usb_init(void)
{
int ret = 0;
@@ -619,7 +624,7 @@ static int __init alchemy_usb_init(void)
}
if (!ret)
- register_syscore_ops(&alchemy_usb_pm_ops);
+ register_syscore(&alchemy_usb_pm_syscore);
return ret;
}
diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c
index a7bd32e9831b..3d0d468d93a5 100644
--- a/arch/mips/alchemy/common/vss.c
+++ b/arch/mips/alchemy/common/vss.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Au1300 media block power gating (VSS)
*
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 9da3659a9d1c..10a52283f022 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
#
# Alchemy Develboards
#
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index c1a2daaf300a..8df0ccdc9287 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
*
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 7f99592cf56b..6984cd5169b5 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -1,38 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DBAu1000/1500/1100 PBAu1100/1500 board support
*
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
+#include <linux/gpio/property.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/leds.h>
#include <linux/mmc/host.h>
-#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/pm.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
-#include <linux/spi/ads7846.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
@@ -178,14 +165,10 @@ static struct platform_device db1x00_audio_dev = {
/******************************************************************************/
+#ifdef CONFIG_MMC_AU1X
static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
{
- void (*mmc_cd)(struct mmc_host *, unsigned long);
- /* link against CONFIG_MMC=m */
- mmc_cd = symbol_get(mmc_detect_change);
- mmc_cd(ptr, msecs_to_jiffies(500));
- symbol_put(mmc_detect_change);
-
+ mmc_detect_change(ptr, msecs_to_jiffies(500));
return IRQ_HANDLED;
}
@@ -388,17 +371,24 @@ static struct platform_device db1100_mmc1_dev = {
.num_resources = ARRAY_SIZE(au1100_mmc1_res),
.resource = au1100_mmc1_res,
};
+#endif /* CONFIG_MMC_AU1X */
/******************************************************************************/
-static struct ads7846_platform_data db1100_touch_pd = {
- .model = 7846,
- .vref_mv = 3300,
- .gpio_pendown = 21,
+static const struct software_node db1100_alchemy2_gpiochip = {
+ .name = "alchemy-gpio2",
};
-static struct spi_gpio_platform_data db1100_spictl_pd = {
- .num_chipselect = 1,
+static const struct property_entry db1100_ads7846_properties[] = {
+ PROPERTY_ENTRY_U16("ti,vref_min", 3300),
+ PROPERTY_ENTRY_GPIO("pendown-gpios",
+ &db1100_alchemy2_gpiochip, 21, GPIO_ACTIVE_LOW),
+ { }
+};
+
+static const struct software_node db1100_ads7846_swnode = {
+ .name = "ads7846",
+ .properties = db1100_ads7846_properties,
};
static struct spi_board_info db1100_spi_info[] __initdata = {
@@ -409,37 +399,37 @@ static struct spi_board_info db1100_spi_info[] __initdata = {
.chip_select = 0,
.mode = 0,
.irq = AU1100_GPIO21_INT,
- .platform_data = &db1100_touch_pd,
+ .swnode = &db1100_ads7846_swnode,
},
};
-static struct platform_device db1100_spi_dev = {
- .name = "spi_gpio",
- .id = 0,
- .dev = {
- .platform_data = &db1100_spictl_pd,
- .dma_mask = &au1xxx_all_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
+static const struct spi_gpio_platform_data db1100_spictl_pd __initconst = {
+ .num_chipselect = 1,
};
/*
* Alchemy GPIO 2 has its base at 200 so the GPIO lines
* 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
*/
-static struct gpiod_lookup_table db1100_spi_gpiod_table = {
- .dev_id = "spi_gpio",
- .table = {
- GPIO_LOOKUP("alchemy-gpio2", 9,
- "sck", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("alchemy-gpio2", 8,
- "mosi", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("alchemy-gpio2", 7,
- "miso", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("alchemy-gpio2", 10,
- "cs", GPIO_ACTIVE_HIGH),
- { },
- },
+static const struct property_entry db1100_spi_dev_properties[] __initconst = {
+ PROPERTY_ENTRY_GPIO("miso-gpios",
+ &db1100_alchemy2_gpiochip, 7, GPIO_ACTIVE_HIGH),
+ PROPERTY_ENTRY_GPIO("mosi-gpios",
+ &db1100_alchemy2_gpiochip, 8, GPIO_ACTIVE_HIGH),
+ PROPERTY_ENTRY_GPIO("sck-gpios",
+ &db1100_alchemy2_gpiochip, 9, GPIO_ACTIVE_HIGH),
+ PROPERTY_ENTRY_GPIO("cs-gpios",
+ &db1100_alchemy2_gpiochip, 10, GPIO_ACTIVE_HIGH),
+ { }
+};
+
+static const struct platform_device_info db1100_spi_dev_info __initconst = {
+ .name = "spi_gpio",
+ .id = 0,
+ .data = &db1100_spictl_pd,
+ .size_data = sizeof(db1100_spictl_pd),
+ .dma_mask = DMA_BIT_MASK(32),
+ .properties = db1100_spi_dev_properties,
};
static struct platform_device *db1x00_devs[] = {
@@ -451,16 +441,20 @@ static struct platform_device *db1x00_devs[] = {
static struct platform_device *db1100_devs[] = {
&au1100_lcd_device,
+#ifdef CONFIG_MMC_AU1X
&db1100_mmc0_dev,
&db1100_mmc1_dev,
+#endif
};
int __init db1000_dev_setup(void)
{
int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
+ int err;
unsigned long pfc;
struct clk *c, *p;
+ struct platform_device *spi_dev;
if (board == BCSR_WHOAMI_DB1500) {
c0 = AU1500_GPIO2_INT;
@@ -487,6 +481,7 @@ int __init db1000_dev_setup(void)
pfc |= (1 << 0); /* SSI0 pins as GPIOs */
alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
+ software_node_register(&db1100_alchemy2_gpiochip);
spi_register_board_info(db1100_spi_info,
ARRAY_SIZE(db1100_spi_info));
@@ -503,8 +498,11 @@ int __init db1000_dev_setup(void)
clk_put(p);
platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
- gpiod_add_lookup_table(&db1100_spi_gpiod_table);
- platform_device_register(&db1100_spi_dev);
+
+ spi_dev = platform_device_register_full(&db1100_spi_dev_info);
+ err = PTR_ERR_OR_ZERO(spi_dev);
+ if (err)
+ pr_err("failed to register SPI controller: %d\n", err);
} else if (board == BCSR_WHOAMI_DB1000) {
c0 = AU1000_GPIO2_INT;
c1 = AU1000_GPIO5_INT;
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index fb11c578e178..67f067706af2 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -1,21 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DBAu1200/PBAu1200 board platform device registration
*
* Copyright (C) 2008-2011 Manuel Lauss
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/clk.h>
@@ -23,7 +10,6 @@
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/init.h>
-#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/leds.h>
@@ -340,6 +326,7 @@ static struct platform_device db1200_ide_dev = {
/**********************************************************************/
+#ifdef CONFIG_MMC_AU1X
/* SD carddetects: they're supposed to be edge-triggered, but ack
* doesn't seem to work (CPLD Rev 2). Instead, the screaming one
* is disabled and its counterpart enabled. The 200ms timeout is
@@ -353,14 +340,7 @@ static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
{
- void (*mmc_cd)(struct mmc_host *, unsigned long);
-
- /* link against CONFIG_MMC=m */
- mmc_cd = symbol_get(mmc_detect_change);
- if (mmc_cd) {
- mmc_cd(ptr, msecs_to_jiffies(200));
- symbol_put(mmc_detect_change);
- }
+ mmc_detect_change(ptr, msecs_to_jiffies(200));
msleep(100); /* debounce */
if (irq == DB1200_SD0_INSERT_INT)
@@ -444,14 +424,7 @@ static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
{
- void (*mmc_cd)(struct mmc_host *, unsigned long);
-
- /* link against CONFIG_MMC=m */
- mmc_cd = symbol_get(mmc_detect_change);
- if (mmc_cd) {
- mmc_cd(ptr, msecs_to_jiffies(200));
- symbol_put(mmc_detect_change);
- }
+ mmc_detect_change(ptr, msecs_to_jiffies(200));
msleep(100); /* debounce */
if (irq == PB1200_SD1_INSERT_INT)
@@ -612,6 +585,7 @@ static struct platform_device pb1200_mmc1_dev = {
.num_resources = ARRAY_SIZE(au1200_mmc1_res),
.resource = au1200_mmc1_res,
};
+#endif /* CONFIG_MMC_AU1X */
/**********************************************************************/
@@ -779,7 +753,9 @@ static struct platform_device db1200_audiodma_dev = {
static struct platform_device *db1200_devs[] __initdata = {
NULL, /* PSC0, selected by S6.8 */
&db1200_ide_dev,
+#ifdef CONFIG_MMC_AU1X
&db1200_mmc0_dev,
+#endif
&au1200_lcd_dev,
&db1200_eth_dev,
&db1200_nand_dev,
@@ -790,7 +766,9 @@ static struct platform_device *db1200_devs[] __initdata = {
};
static struct platform_device *pb1200_devs[] __initdata = {
+#ifdef CONFIG_MMC_AU1X
&pb1200_mmc1_dev,
+#endif
};
/* Some peripheral base addresses differ on the PB1200 */
@@ -848,7 +826,7 @@ int __init db1200_dev_setup(void)
if (!IS_ERR(c)) {
pfc = clk_round_rate(c, 50000000);
if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
- pr_warn("DB1200: cant get I2C close to 50MHz\n");
+ pr_warn("DB1200: can't get I2C close to 50MHz\n");
else
clk_set_rate(c, pfc);
clk_prepare_enable(c);
@@ -869,7 +847,7 @@ int __init db1200_dev_setup(void)
i2c_register_board_info(0, db1200_i2c_devs,
ARRAY_SIZE(db1200_i2c_devs));
spi_register_board_info(db1200_spi_devs,
- ARRAY_SIZE(db1200_i2c_devs));
+ ARRAY_SIZE(db1200_spi_devs));
/* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
* S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index 8ac1f56ee57d..d377e043b49f 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -17,7 +17,6 @@
#include <linux/interrupt.h>
#include <linux/ata_platform.h>
#include <linux/mmc/host.h>
-#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/platnand.h>
#include <linux/platform_device.h>
@@ -451,6 +450,7 @@ static struct platform_device db1300_ide_dev = {
/**********************************************************************/
+#ifdef CONFIG_MMC_AU1X
static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
{
disable_irq_nosync(irq);
@@ -459,14 +459,7 @@ static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr)
{
- void (*mmc_cd)(struct mmc_host *, unsigned long);
-
- /* link against CONFIG_MMC=m. We can only be called once MMC core has
- * initialized the controller, so symbol_get() should always succeed.
- */
- mmc_cd = symbol_get(mmc_detect_change);
- mmc_cd(ptr, msecs_to_jiffies(200));
- symbol_put(mmc_detect_change);
+ mmc_detect_change(ptr, msecs_to_jiffies(200));
msleep(100); /* debounce */
if (irq == DB1300_SD1_INSERT_INT)
@@ -640,6 +633,7 @@ static struct platform_device db1300_sd0_dev = {
.resource = au1300_sd0_res,
.num_resources = ARRAY_SIZE(au1300_sd0_res),
};
+#endif /* CONFIG_MMC_AU1X */
/**********************************************************************/
@@ -731,16 +725,8 @@ static struct platform_device db1300_lcd_dev = {
/**********************************************************************/
-static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable)
-{
- if (enable)
- enable_irq(DB1300_AC97_PEN_INT);
- else
- disable_irq_nosync(DB1300_AC97_PEN_INT);
-}
-
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_WM97XX)
static struct wm97xx_mach_ops db1300_wm97xx_ops = {
- .irq_enable = db1300_wm97xx_irqen,
.irq_gpio = WM97XX_GPIO_3,
};
@@ -762,6 +748,12 @@ static int db1300_wm97xx_probe(struct platform_device *pdev)
return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops);
}
+#else
+static int db1300_wm97xx_probe(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
+#endif
static struct platform_driver db1300_wm97xx_driver = {
.driver.name = "wm97xx-touch",
@@ -777,8 +769,10 @@ static struct platform_device *db1300_dev[] __initdata = {
&db1300_5waysw_dev,
&db1300_nand_dev,
&db1300_ide_dev,
+#ifdef CONFIG_MMC_AU1X
&db1300_sd0_dev,
&db1300_sd1_dev,
+#endif
&db1300_lcd_dev,
&db1300_ac97_dev,
&db1300_i2s_dev,
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
index 3e0c75c0ece0..6c6837181f55 100644
--- a/arch/mips/alchemy/devboards/db1550.c
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -66,6 +66,7 @@ int __init db1550_board_setup(void)
case BCSR_WHOAMI_PB1550_DDR:
bcsr_init(PB1550_BCSR_PHYS_ADDR,
PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
+ break;
case BCSR_WHOAMI_DB1550:
break;
default:
@@ -225,7 +226,7 @@ static void __init pb1550_nand_setup(void)
case 0: case 2: case 8: case 0xC: case 0xD:
/* x16 NAND Flash */
pb1550_nand_pd.devwidth = 1;
- /* fallthrough */
+ fallthrough;
case 1: case 3: case 9: case 0xE: case 0xF:
/* x8 NAND, already set up */
platform_device_register(&pb1550_nand_dev);
@@ -588,7 +589,7 @@ int __init db1550_dev_setup(void)
i2c_register_board_info(0, db1550_i2c_devs,
ARRAY_SIZE(db1550_i2c_devs));
spi_register_board_info(db1550_spi_devs,
- ARRAY_SIZE(db1550_i2c_devs));
+ ARRAY_SIZE(db1550_spi_devs));
c = clk_get(NULL, "psc0_intclk");
if (!IS_ERR(c)) {
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index 8d4b65c3268a..754bdd2ca630 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -20,23 +20,6 @@
#include <prom.h>
-void __init prom_init(void)
-{
- unsigned char *memsize_str;
- unsigned long memsize;
-
- prom_argc = (int)fw_arg0;
- prom_argv = (char **)fw_arg1;
- prom_envp = (char **)fw_arg2;
-
- prom_init_cmdline();
- memsize_str = prom_getenv("memsize");
- if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
- memsize = 64 << 20; /* all devboards have at least 64MB RAM */
-
- add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
void prom_putchar(char c)
{
if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300)
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index 73c77814687a..b17a0d199851 100644
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -17,7 +17,7 @@
* Generic suspend userspace interface for Alchemy development boards.
* This code exports a few sysfs nodes under /sys/power/db1x/ which
* can be used by userspace to en/disable all au1x-provided wakeup
- * sources and configure the timeout after which the the TOYMATCH2 irq
+ * sources and configure the timeout after which the TOYMATCH2 irq
* is to trigger a wakeup.
*/