diff options
Diffstat (limited to 'arch/tile/include/arch')
| -rw-r--r-- | arch/tile/include/arch/mpipe.h | 371 | ||||
| -rw-r--r-- | arch/tile/include/arch/mpipe_constants.h | 42 | ||||
| -rw-r--r-- | arch/tile/include/arch/mpipe_def.h | 39 | ||||
| -rw-r--r-- | arch/tile/include/arch/mpipe_shm.h | 521 | ||||
| -rw-r--r-- | arch/tile/include/arch/mpipe_shm_def.h | 23 | ||||
| -rw-r--r-- | arch/tile/include/arch/spr_def.h | 109 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio.h | 111 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_constants.h | 36 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_def.h | 41 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_pcie_intfc.h | 229 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_pcie_intfc_def.h | 32 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_pcie_rc.h | 156 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_pcie_rc_def.h | 24 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_shm.h | 125 | ||||
| -rw-r--r-- | arch/tile/include/arch/trio_shm_def.h | 19 | ||||
| -rw-r--r-- | arch/tile/include/arch/uart.h | 300 | ||||
| -rw-r--r-- | arch/tile/include/arch/uart_def.h | 120 | ||||
| -rw-r--r-- | arch/tile/include/arch/usb_host.h | 26 | ||||
| -rw-r--r-- | arch/tile/include/arch/usb_host_def.h | 19 |
19 files changed, 0 insertions, 2343 deletions
diff --git a/arch/tile/include/arch/mpipe.h b/arch/tile/include/arch/mpipe.h deleted file mode 100644 index 904538e754d8..000000000000 --- a/arch/tile/include/arch/mpipe.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_MPIPE_H__ -#define __ARCH_MPIPE_H__ - -#include <arch/abi.h> -#include <arch/mpipe_def.h> - -#ifndef __ASSEMBLER__ - -/* - * MMIO Ingress DMA Release Region Address. - * This is a description of the physical addresses used to manipulate ingress - * credit counters. Accesses to this address space should use an address of - * this form and a value like that specified in IDMA_RELEASE_REGION_VAL. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Reserved. */ - uint_reg_t __reserved_0 : 3; - /* NotifRing to be released */ - uint_reg_t ring : 8; - /* Bucket to be released */ - uint_reg_t bucket : 13; - /* Enable NotifRing release */ - uint_reg_t ring_enable : 1; - /* Enable Bucket release */ - uint_reg_t bucket_enable : 1; - /* - * This field of the address selects the region (address space) to be - * accessed. For the iDMA release region, this field must be 4. - */ - uint_reg_t region : 3; - /* Reserved. */ - uint_reg_t __reserved_1 : 6; - /* This field of the address indexes the 32 entry service domain table. */ - uint_reg_t svc_dom : 5; - /* Reserved. */ - uint_reg_t __reserved_2 : 24; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_2 : 24; - uint_reg_t svc_dom : 5; - uint_reg_t __reserved_1 : 6; - uint_reg_t region : 3; - uint_reg_t bucket_enable : 1; - uint_reg_t ring_enable : 1; - uint_reg_t bucket : 13; - uint_reg_t ring : 8; - uint_reg_t __reserved_0 : 3; -#endif - }; - - uint_reg_t word; -} MPIPE_IDMA_RELEASE_REGION_ADDR_t; - -/* - * MMIO Ingress DMA Release Region Value - Release NotifRing and/or Bucket. - * Provides release of the associated NotifRing. The address of the MMIO - * operation is described in IDMA_RELEASE_REGION_ADDR. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * Number of packets being released. The load balancer's count of - * inflight packets will be decremented by this amount for the associated - * Bucket and/or NotifRing - */ - uint_reg_t count : 16; - /* Reserved. */ - uint_reg_t __reserved : 48; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved : 48; - uint_reg_t count : 16; -#endif - }; - - uint_reg_t word; -} MPIPE_IDMA_RELEASE_REGION_VAL_t; - -/* - * MMIO Buffer Stack Manager Region Address. - * This MMIO region is used for posting or fetching buffers to/from the - * buffer stack manager. On an MMIO load, this pops a buffer descriptor from - * the top of stack if one is available. On an MMIO store, this pushes a - * buffer to the stack. The value read or written is described in - * BSM_REGION_VAL. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Reserved. */ - uint_reg_t __reserved_0 : 3; - /* BufferStack being accessed. */ - uint_reg_t stack : 5; - /* Reserved. */ - uint_reg_t __reserved_1 : 18; - /* - * This field of the address selects the region (address space) to be - * accessed. For the buffer stack manager region, this field must be 6. - */ - uint_reg_t region : 3; - /* Reserved. */ - uint_reg_t __reserved_2 : 6; - /* This field of the address indexes the 32 entry service domain table. */ - uint_reg_t svc_dom : 5; - /* Reserved. */ - uint_reg_t __reserved_3 : 24; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_3 : 24; - uint_reg_t svc_dom : 5; - uint_reg_t __reserved_2 : 6; - uint_reg_t region : 3; - uint_reg_t __reserved_1 : 18; - uint_reg_t stack : 5; - uint_reg_t __reserved_0 : 3; -#endif - }; - - uint_reg_t word; -} MPIPE_BSM_REGION_ADDR_t; - -/* - * MMIO Buffer Stack Manager Region Value. - * This MMIO region is used for posting or fetching buffers to/from the - * buffer stack manager. On an MMIO load, this pops a buffer descriptor from - * the top of stack if one is available. On an MMIO store, this pushes a - * buffer to the stack. The address of the MMIO operation is described in - * BSM_REGION_ADDR. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Reserved. */ - uint_reg_t __reserved_0 : 7; - /* - * Base virtual address of the buffer. Must be sign extended by consumer. - */ - int_reg_t va : 35; - /* Reserved. */ - uint_reg_t __reserved_1 : 6; - /* - * Index of the buffer stack to which this buffer belongs. Ignored on - * writes since the offset bits specify the stack being accessed. - */ - uint_reg_t stack_idx : 5; - /* Reserved. */ - uint_reg_t __reserved_2 : 3; - /* - * Instance ID. For devices that support automatic buffer return between - * mPIPE instances, this field indicates the buffer owner. If the INST - * field does not match the mPIPE's instance number when a packet is - * egressed, buffers with HWB set will be returned to the other mPIPE - * instance. Note that not all devices support multi-mPIPE buffer - * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates - * whether the INST field in the buffer descriptor is populated by iDMA - * hardware. This field is ignored on writes. - */ - uint_reg_t inst : 2; - /* - * Reads as one to indicate that this is a hardware managed buffer. - * Ignored on writes since all buffers on a given stack are the same size. - */ - uint_reg_t hwb : 1; - /* - * Encoded size of buffer (ignored on writes): - * 0 = 128 bytes - * 1 = 256 bytes - * 2 = 512 bytes - * 3 = 1024 bytes - * 4 = 1664 bytes - * 5 = 4096 bytes - * 6 = 10368 bytes - * 7 = 16384 bytes - */ - uint_reg_t size : 3; - /* - * Valid indication for the buffer. Ignored on writes. - * 0 : Valid buffer descriptor popped from stack. - * 3 : Could not pop a buffer from the stack. Either the stack is empty, - * or the hardware's prefetch buffer is empty for this stack. - */ - uint_reg_t c : 2; -#else /* __BIG_ENDIAN__ */ - uint_reg_t c : 2; - uint_reg_t size : 3; - uint_reg_t hwb : 1; - uint_reg_t inst : 2; - uint_reg_t __reserved_2 : 3; - uint_reg_t stack_idx : 5; - uint_reg_t __reserved_1 : 6; - int_reg_t va : 35; - uint_reg_t __reserved_0 : 7; -#endif - }; - - uint_reg_t word; -} MPIPE_BSM_REGION_VAL_t; - -/* - * MMIO Egress DMA Post Region Address. - * Used to post descriptor locations to the eDMA descriptor engine. The - * value to be written is described in EDMA_POST_REGION_VAL - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Reserved. */ - uint_reg_t __reserved_0 : 3; - /* eDMA ring being accessed */ - uint_reg_t ring : 6; - /* Reserved. */ - uint_reg_t __reserved_1 : 17; - /* - * This field of the address selects the region (address space) to be - * accessed. For the egress DMA post region, this field must be 5. - */ - uint_reg_t region : 3; - /* Reserved. */ - uint_reg_t __reserved_2 : 6; - /* This field of the address indexes the 32 entry service domain table. */ - uint_reg_t svc_dom : 5; - /* Reserved. */ - uint_reg_t __reserved_3 : 24; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_3 : 24; - uint_reg_t svc_dom : 5; - uint_reg_t __reserved_2 : 6; - uint_reg_t region : 3; - uint_reg_t __reserved_1 : 17; - uint_reg_t ring : 6; - uint_reg_t __reserved_0 : 3; -#endif - }; - - uint_reg_t word; -} MPIPE_EDMA_POST_REGION_ADDR_t; - -/* - * MMIO Egress DMA Post Region Value. - * Used to post descriptor locations to the eDMA descriptor engine. The - * address is described in EDMA_POST_REGION_ADDR. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * For writes, this specifies the current ring tail pointer prior to any - * post. For example, to post 1 or more descriptors starting at location - * 23, this would contain 23 (not 24). On writes, this index must be - * masked based on the ring size. The new tail pointer after this post - * is COUNT+RING_IDX (masked by the ring size). - * - * For reads, this provides the hardware descriptor fetcher's head - * pointer. The descriptors prior to the head pointer, however, may not - * yet have been processed so this indicator is only used to determine - * how full the ring is and if software may post more descriptors. - */ - uint_reg_t ring_idx : 16; - /* - * For writes, this specifies number of contiguous descriptors that are - * being posted. Software may post up to RingSize descriptors with a - * single MMIO store. A zero in this field on a write will "wake up" an - * eDMA ring and cause it fetch descriptors regardless of the hardware's - * current view of the state of the tail pointer. - * - * For reads, this field provides a rolling count of the number of - * descriptors that have been completely processed. This may be used by - * software to determine when buffers associated with a descriptor may be - * returned or reused. When the ring's flush bit is cleared by software - * (after having been set by HW or SW), the COUNT will be cleared. - */ - uint_reg_t count : 16; - /* - * For writes, this specifies the generation number of the tail being - * posted. Note that if tail+cnt wraps to the beginning of the ring, the - * eDMA hardware assumes that the descriptors posted at the beginning of - * the ring are also valid so it is okay to post around the wrap point. - * - * For reads, this is the current generation number. Valid descriptors - * will have the inverse of this generation number. - */ - uint_reg_t gen : 1; - /* Reserved. */ - uint_reg_t __reserved : 31; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved : 31; - uint_reg_t gen : 1; - uint_reg_t count : 16; - uint_reg_t ring_idx : 16; -#endif - }; - - uint_reg_t word; -} MPIPE_EDMA_POST_REGION_VAL_t; - -/* - * Load Balancer Bucket Status Data. - * Read/Write data for load balancer Bucket-Status Table. 4160 entries - * indexed by LBL_INIT_CTL.IDX when LBL_INIT_CTL.STRUCT_SEL is BSTS_TBL - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* NotifRing currently assigned to this bucket. */ - uint_reg_t notifring : 8; - /* Current reference count. */ - uint_reg_t count : 16; - /* Group associated with this bucket. */ - uint_reg_t group : 5; - /* Mode select for this bucket. */ - uint_reg_t mode : 3; - /* Reserved. */ - uint_reg_t __reserved : 32; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved : 32; - uint_reg_t mode : 3; - uint_reg_t group : 5; - uint_reg_t count : 16; - uint_reg_t notifring : 8; -#endif - }; - - uint_reg_t word; -} MPIPE_LBL_INIT_DAT_BSTS_TBL_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_MPIPE_H__) */ diff --git a/arch/tile/include/arch/mpipe_constants.h b/arch/tile/include/arch/mpipe_constants.h deleted file mode 100644 index 84022ac5fe82..000000000000 --- a/arch/tile/include/arch/mpipe_constants.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - - -#ifndef __ARCH_MPIPE_CONSTANTS_H__ -#define __ARCH_MPIPE_CONSTANTS_H__ - -#define MPIPE_NUM_CLASSIFIERS 16 -#define MPIPE_CLS_MHZ 1200 - -#define MPIPE_NUM_EDMA_RINGS 64 - -#define MPIPE_NUM_SGMII_MACS 16 -#define MPIPE_NUM_XAUI_MACS 16 -#define MPIPE_NUM_LOOPBACK_CHANNELS 4 -#define MPIPE_NUM_NON_LB_CHANNELS 28 - -#define MPIPE_NUM_IPKT_BLOCKS 1536 - -#define MPIPE_NUM_BUCKETS 4160 - -#define MPIPE_NUM_NOTIF_RINGS 256 - -#define MPIPE_NUM_NOTIF_GROUPS 32 - -#define MPIPE_NUM_TLBS_PER_ASID 16 -#define MPIPE_TLB_IDX_WIDTH 4 - -#define MPIPE_MMIO_NUM_SVC_DOM 32 - -#endif /* __ARCH_MPIPE_CONSTANTS_H__ */ diff --git a/arch/tile/include/arch/mpipe_def.h b/arch/tile/include/arch/mpipe_def.h deleted file mode 100644 index c3d30217fc66..000000000000 --- a/arch/tile/include/arch/mpipe_def.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_MPIPE_DEF_H__ -#define __ARCH_MPIPE_DEF_H__ -#define MPIPE_MMIO_ADDR__REGION_SHIFT 26 -#define MPIPE_MMIO_ADDR__REGION_VAL_CFG 0x0 -#define MPIPE_MMIO_ADDR__REGION_VAL_IDMA 0x4 -#define MPIPE_MMIO_ADDR__REGION_VAL_EDMA 0x5 -#define MPIPE_MMIO_ADDR__REGION_VAL_BSM 0x6 -#define MPIPE_BSM_REGION_VAL__VA_SHIFT 7 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_128 0x0 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_256 0x1 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512 0x2 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1024 0x3 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1664 0x4 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_4096 0x5 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_10368 0x6 -#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_16384 0x7 -#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_DFA 0x0 -#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_FIXED 0x1 -#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK 0x2 -#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY 0x3 -#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY_RAND 0x7 -#define MPIPE_LBL_NR_STATE__FIRST_WORD 0x2138 -#endif /* !defined(__ARCH_MPIPE_DEF_H__) */ diff --git a/arch/tile/include/arch/mpipe_shm.h b/arch/tile/include/arch/mpipe_shm.h deleted file mode 100644 index 13b3c4300e50..000000000000 --- a/arch/tile/include/arch/mpipe_shm.h +++ /dev/null @@ -1,521 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - - -#ifndef __ARCH_MPIPE_SHM_H__ -#define __ARCH_MPIPE_SHM_H__ - -#include <arch/abi.h> -#include <arch/mpipe_shm_def.h> - -#ifndef __ASSEMBLER__ -/** - * MPIPE eDMA Descriptor. - * The eDMA descriptor is written by software and consumed by hardware. It - * is used to specify the location of egress packet data to be sent out of - * the chip via one of the packet interfaces. - */ - -__extension__ -typedef union -{ - struct - { - /* Word 0 */ - -#ifndef __BIG_ENDIAN__ - /** - * Generation number. Used to indicate a valid descriptor in ring. When - * a new descriptor is written into the ring, software must toggle this - * bit. The net effect is that the GEN bit being written into new - * descriptors toggles each time the ring tail pointer wraps. - */ - uint_reg_t gen : 1; - /** - * For devices with EDMA reorder support, this field allows the - * descriptor to select the egress FIFO. The associated DMA ring must - * have ALLOW_EFIFO_SEL enabled. - */ - uint_reg_t efifo_sel : 6; - /** Reserved. Must be zero. */ - uint_reg_t r0 : 1; - /** Checksum generation enabled for this transfer. */ - uint_reg_t csum : 1; - /** - * Nothing to be sent. Used, for example, when software has dropped a - * packet but still wishes to return all of the associated buffers. - */ - uint_reg_t ns : 1; - /** - * Notification interrupt will be delivered when packet has been egressed. - */ - uint_reg_t notif : 1; - /** - * Boundary indicator. When 1, this transfer includes the EOP for this - * command. Must be clear on all but the last descriptor for an egress - * packet. - */ - uint_reg_t bound : 1; - /** Reserved. Must be zero. */ - uint_reg_t r1 : 4; - /** - * Number of bytes to be sent for this descriptor. When zero, no data - * will be moved and the buffer descriptor will be ignored. If the - * buffer descriptor indicates that it is chained, the low 7 bits of the - * VA indicate the offset within the first buffer (e.g. 127 bytes is the - * maximum offset into the first buffer). If the size exceeds a single - * buffer, subsequent buffer descriptors will be fetched prior to - * processing the next eDMA descriptor in the ring. - */ - uint_reg_t xfer_size : 14; - /** Reserved. Must be zero. */ - uint_reg_t r2 : 2; - /** - * Destination of checksum relative to CSUM_START relative to the first - * byte moved by this descriptor. Must be zero if CSUM=0 in this - * descriptor. Must be less than XFER_SIZE (e.g. the first byte of the - * CSUM_DEST must be within the span of this descriptor). - */ - uint_reg_t csum_dest : 8; - /** - * Start byte of checksum relative to the first byte moved by this - * descriptor. If this is not the first descriptor for the egress - * packet, CSUM_START is still relative to the first byte in this - * descriptor. Must be zero if CSUM=0 in this descriptor. - */ - uint_reg_t csum_start : 8; - /** - * Initial value for 16-bit 1's compliment checksum if enabled via CSUM. - * Specified in network order. That is, bits[7:0] will be added to the - * byte pointed to by CSUM_START and bits[15:8] will be added to the byte - * pointed to by CSUM_START+1 (with appropriate 1's compliment carries). - * Must be zero if CSUM=0 in this descriptor. - */ - uint_reg_t csum_seed : 16; -#else /* __BIG_ENDIAN__ */ - uint_reg_t csum_seed : 16; - uint_reg_t csum_start : 8; - uint_reg_t csum_dest : 8; - uint_reg_t r2 : 2; - uint_reg_t xfer_size : 14; - uint_reg_t r1 : 4; - uint_reg_t bound : 1; - uint_reg_t notif : 1; - uint_reg_t ns : 1; - uint_reg_t csum : 1; - uint_reg_t r0 : 1; - uint_reg_t efifo_sel : 6; - uint_reg_t gen : 1; -#endif - - /* Word 1 */ - -#ifndef __BIG_ENDIAN__ - /** Virtual address. Must be sign extended by consumer. */ - int_reg_t va : 42; - /** Reserved. */ - uint_reg_t __reserved_0 : 6; - /** Index of the buffer stack to which this buffer belongs. */ - uint_reg_t stack_idx : 5; - /** Reserved. */ - uint_reg_t __reserved_1 : 3; - /** - * Instance ID. For devices that support automatic buffer return between - * mPIPE instances, this field indicates the buffer owner. If the INST - * field does not match the mPIPE's instance number when a packet is - * egressed, buffers with HWB set will be returned to the other mPIPE - * instance. Note that not all devices support multi-mPIPE buffer - * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates - * whether the INST field in the buffer descriptor is populated by iDMA - * hardware. - */ - uint_reg_t inst : 2; - /** - * Always set to one by hardware in iDMA packet descriptors. For eDMA, - * indicates whether the buffer will be released to the buffer stack - * manager. When 0, software is responsible for releasing the buffer. - */ - uint_reg_t hwb : 1; - /** - * Encoded size of buffer. Set by the ingress hardware for iDMA packet - * descriptors. For eDMA descriptors, indicates the buffer size if .c - * indicates a chained packet. If an eDMA descriptor is not chained and - * the .hwb bit is not set, this field is ignored and the size is - * specified by the .xfer_size field. - * 0 = 128 bytes - * 1 = 256 bytes - * 2 = 512 bytes - * 3 = 1024 bytes - * 4 = 1664 bytes - * 5 = 4096 bytes - * 6 = 10368 bytes - * 7 = 16384 bytes - */ - uint_reg_t size : 3; - /** - * Chaining configuration for the buffer. Indicates that an ingress - * packet or egress command is chained across multiple buffers, with each - * buffer's size indicated by the .size field. - */ - uint_reg_t c : 2; -#else /* __BIG_ENDIAN__ */ - uint_reg_t c : 2; - uint_reg_t size : 3; - uint_reg_t hwb : 1; - uint_reg_t inst : 2; - uint_reg_t __reserved_1 : 3; - uint_reg_t stack_idx : 5; - uint_reg_t __reserved_0 : 6; - int_reg_t va : 42; -#endif - - }; - - /** Word access */ - uint_reg_t words[2]; -} MPIPE_EDMA_DESC_t; - -/** - * MPIPE Packet Descriptor. - * The packet descriptor is filled by the mPIPE's classification, - * load-balancing, and buffer management services. Some fields are consumed - * by mPIPE hardware, and others are consumed by Tile software. - */ - -__extension__ -typedef union -{ - struct - { - /* Word 0 */ - -#ifndef __BIG_ENDIAN__ - /** - * Notification ring into which this packet descriptor is written. - * Typically written by load balancer, but can be overridden by - * classification program if NR is asserted. - */ - uint_reg_t notif_ring : 8; - /** Source channel for this packet. Written by mPIPE DMA hardware. */ - uint_reg_t channel : 5; - /** Reserved. */ - uint_reg_t __reserved_0 : 1; - /** - * MAC Error. - * Generated by the MAC interface. Asserted if there was an overrun of - * the MAC's receive FIFO. This condition generally only occurs if the - * mPIPE clock is running too slowly. - */ - uint_reg_t me : 1; - /** - * Truncation Error. - * Written by the iDMA hardware. Asserted if packet was truncated due to - * insufficient space in iPkt buffer - */ - uint_reg_t tr : 1; - /** - * Written by the iDMA hardware. Indicates the number of bytes written - * to Tile memory. In general, this is the actual size of the packet as - * received from the MAC. But if the packet is truncated due to running - * out of buffers or due to the iPkt buffer filling up, then the L2_SIZE - * will be reduced to reflect the actual number of valid bytes written to - * Tile memory. - */ - uint_reg_t l2_size : 14; - /** - * CRC Error. - * Generated by the MAC. Asserted if MAC indicated an L2 CRC error or - * other L2 error (bad length etc.) on the packet. - */ - uint_reg_t ce : 1; - /** - * Cut Through. - * Written by the iDMA hardware. Asserted if packet was not completely - * received before being sent to classifier. L2_Size will indicate - * number of bytes received so far. - */ - uint_reg_t ct : 1; - /** - * Written by the classification program. Used by the load balancer to - * select the ring into which this packet descriptor is written. - */ - uint_reg_t bucket_id : 13; - /** Reserved. */ - uint_reg_t __reserved_1 : 3; - /** - * Checksum. - * Written by classification program. When 1, the checksum engine will - * perform checksum based on the CSUM_SEED, CSUM_START, and CSUM_BYTES - * fields. The result will be placed in CSUM_VAL. - */ - uint_reg_t cs : 1; - /** - * Notification Ring Select. - * Written by the classification program. When 1, the NotifRingIDX is - * set by classification program rather than being set by load balancer. - */ - uint_reg_t nr : 1; - /** - * Written by classification program. Indicates whether packet and - * descriptor should both be dropped, both be delivered, or only the - * descriptor should be delivered. - */ - uint_reg_t dest : 2; - /** - * General Purpose Sequence Number Enable. - * Written by the classification program. When 1, the GP_SQN_SEL field - * contains the sequence number selector and the GP_SQN field will be - * replaced with the associated sequence number. When clear, the GP_SQN - * field is left intact and be used as "Custom" bytes. - */ - uint_reg_t sq : 1; - /** - * TimeStamp Enable. - * Enable TimeStamp insertion. When clear, timestamp field may be filled - * with custom data by classifier. When set, hardware inserts the - * timestamp when the start of packet is received from the MAC. - */ - uint_reg_t ts : 1; - /** - * Packet Sequence Number Enable. - * Enable PacketSQN insertion. When clear, PacketSQN field may be filled - * with custom data by classifier. When set, hardware inserts the packet - * sequence number when the packet descriptor is written to a - * notification ring. - */ - uint_reg_t ps : 1; - /** - * Buffer Error. - * Written by the iDMA hardware. Asserted if iDMA ran out of buffers - * while writing the packet. Software must still return any buffer - * descriptors whose C field indicates a valid descriptor was consumed. - */ - uint_reg_t be : 1; - /** - * Written by the classification program. The associated counter is - * incremented when the packet is sent. - */ - uint_reg_t ctr0 : 5; - /** Reserved. */ - uint_reg_t __reserved_2 : 3; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_2 : 3; - uint_reg_t ctr0 : 5; - uint_reg_t be : 1; - uint_reg_t ps : 1; - uint_reg_t ts : 1; - uint_reg_t sq : 1; - uint_reg_t dest : 2; - uint_reg_t nr : 1; - uint_reg_t cs : 1; - uint_reg_t __reserved_1 : 3; - uint_reg_t bucket_id : 13; - uint_reg_t ct : 1; - uint_reg_t ce : 1; - uint_reg_t l2_size : 14; - uint_reg_t tr : 1; - uint_reg_t me : 1; - uint_reg_t __reserved_0 : 1; - uint_reg_t channel : 5; - uint_reg_t notif_ring : 8; -#endif - - /* Word 1 */ - -#ifndef __BIG_ENDIAN__ - /** - * Written by the classification program. The associated counter is - * incremented when the packet is sent. - */ - uint_reg_t ctr1 : 5; - /** Reserved. */ - uint_reg_t __reserved_3 : 3; - /** - * Written by classification program. Indicates the start byte for - * checksum. Relative to 1st byte received from MAC. - */ - uint_reg_t csum_start : 8; - /** - * Checksum seed written by classification program. Overwritten with - * resultant checksum if CS bit is asserted. The endianness of the CSUM - * value bits when viewed by Tile software match the packet byte order. - * That is, bits[7:0] of the resulting checksum value correspond to - * earlier (more significant) bytes in the packet. To avoid classifier - * software from having to byte swap the CSUM_SEED, the iDMA checksum - * engine byte swaps the classifier's result before seeding the checksum - * calculation. Thus, the CSUM_START byte of packet data is added to - * bits[15:8] of the CSUM_SEED field generated by the classifier. This - * byte swap will be visible to Tile software if the CS bit is clear. - */ - uint_reg_t csum_seed_val : 16; - /** - * Written by the classification program. Not interpreted by mPIPE - * hardware. - */ - uint_reg_t custom0 : 32; -#else /* __BIG_ENDIAN__ */ - uint_reg_t custom0 : 32; - uint_reg_t csum_seed_val : 16; - uint_reg_t csum_start : 8; - uint_reg_t __reserved_3 : 3; - uint_reg_t ctr1 : 5; -#endif - - /* Word 2 */ - -#ifndef __BIG_ENDIAN__ - /** - * Written by the classification program. Not interpreted by mPIPE - * hardware. - */ - uint_reg_t custom1 : 64; -#else /* __BIG_ENDIAN__ */ - uint_reg_t custom1 : 64; -#endif - - /* Word 3 */ - -#ifndef __BIG_ENDIAN__ - /** - * Written by the classification program. Not interpreted by mPIPE - * hardware. - */ - uint_reg_t custom2 : 64; -#else /* __BIG_ENDIAN__ */ - uint_reg_t custom2 : 64; -#endif - - /* Word 4 */ - -#ifndef __BIG_ENDIAN__ - /** - * Written by the classification program. Not interpreted by mPIPE - * hardware. - */ - uint_reg_t custom3 : 64; -#else /* __BIG_ENDIAN__ */ - uint_reg_t custom3 : 64; -#endif - - /* Word 5 */ - -#ifndef __BIG_ENDIAN__ - /** - * Sequence number applied when packet is distributed. Classifier - * selects which sequence number is to be applied by writing the 13-bit - * SQN-selector into this field. For devices that support EXT_SQN (as - * indicated in IDMA_INFO.EXT_SQN_SUPPORT), the GP_SQN can be extended to - * 32-bits via the IDMA_CTL.EXT_SQN register. In this case the - * PACKET_SQN will be reduced to 32 bits. - */ - uint_reg_t gp_sqn : 16; - /** - * Written by notification hardware. The packet sequence number is - * incremented for each packet that wasn't dropped. - */ - uint_reg_t packet_sqn : 48; -#else /* __BIG_ENDIAN__ */ - uint_reg_t packet_sqn : 48; - uint_reg_t gp_sqn : 16; -#endif - - /* Word 6 */ - -#ifndef __BIG_ENDIAN__ - /** - * Written by hardware when the start-of-packet is received by the mPIPE - * from the MAC. This is the nanoseconds part of the packet timestamp. - */ - uint_reg_t time_stamp_ns : 32; - /** - * Written by hardware when the start-of-packet is received by the mPIPE - * from the MAC. This is the seconds part of the packet timestamp. - */ - uint_reg_t time_stamp_sec : 32; -#else /* __BIG_ENDIAN__ */ - uint_reg_t time_stamp_sec : 32; - uint_reg_t time_stamp_ns : 32; -#endif - - /* Word 7 */ - -#ifndef __BIG_ENDIAN__ - /** Virtual address. Must be sign extended by consumer. */ - int_reg_t va : 42; - /** Reserved. */ - uint_reg_t __reserved_4 : 6; - /** Index of the buffer stack to which this buffer belongs. */ - uint_reg_t stack_idx : 5; - /** Reserved. */ - uint_reg_t __reserved_5 : 3; - /** - * Instance ID. For devices that support automatic buffer return between - * mPIPE instances, this field indicates the buffer owner. If the INST - * field does not match the mPIPE's instance number when a packet is - * egressed, buffers with HWB set will be returned to the other mPIPE - * instance. Note that not all devices support multi-mPIPE buffer - * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates - * whether the INST field in the buffer descriptor is populated by iDMA - * hardware. - */ - uint_reg_t inst : 2; - /** - * Always set to one by hardware in iDMA packet descriptors. For eDMA, - * indicates whether the buffer will be released to the buffer stack - * manager. When 0, software is responsible for releasing the buffer. - */ - uint_reg_t hwb : 1; - /** - * Encoded size of buffer. Set by the ingress hardware for iDMA packet - * descriptors. For eDMA descriptors, indicates the buffer size if .c - * indicates a chained packet. If an eDMA descriptor is not chained and - * the .hwb bit is not set, this field is ignored and the size is - * specified by the .xfer_size field. - * 0 = 128 bytes - * 1 = 256 bytes - * 2 = 512 bytes - * 3 = 1024 bytes - * 4 = 1664 bytes - * 5 = 4096 bytes - * 6 = 10368 bytes - * 7 = 16384 bytes - */ - uint_reg_t size : 3; - /** - * Chaining configuration for the buffer. Indicates that an ingress - * packet or egress command is chained across multiple buffers, with each - * buffer's size indicated by the .size field. - */ - uint_reg_t c : 2; -#else /* __BIG_ENDIAN__ */ - uint_reg_t c : 2; - uint_reg_t size : 3; - uint_reg_t hwb : 1; - uint_reg_t inst : 2; - uint_reg_t __reserved_5 : 3; - uint_reg_t stack_idx : 5; - uint_reg_t __reserved_4 : 6; - int_reg_t va : 42; -#endif - - }; - - /** Word access */ - uint_reg_t words[8]; -} MPIPE_PDESC_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_MPIPE_SHM_H__) */ diff --git a/arch/tile/include/arch/mpipe_shm_def.h b/arch/tile/include/arch/mpipe_shm_def.h deleted file mode 100644 index 6124d39c8318..000000000000 --- a/arch/tile/include/arch/mpipe_shm_def.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_MPIPE_SHM_DEF_H__ -#define __ARCH_MPIPE_SHM_DEF_H__ -#define MPIPE_EDMA_DESC_WORD1__C_VAL_UNCHAINED 0x0 -#define MPIPE_EDMA_DESC_WORD1__C_VAL_CHAINED 0x1 -#define MPIPE_EDMA_DESC_WORD1__C_VAL_NOT_RDY 0x2 -#define MPIPE_EDMA_DESC_WORD1__C_VAL_INVALID 0x3 -#endif /* !defined(__ARCH_MPIPE_SHM_DEF_H__) */ diff --git a/arch/tile/include/arch/spr_def.h b/arch/tile/include/arch/spr_def.h deleted file mode 100644 index 2de83e7aff3e..000000000000 --- a/arch/tile/include/arch/spr_def.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2010 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ -#ifndef __ARCH_SPR_DEF_H__ -#define __ARCH_SPR_DEF_H__ - -#include <uapi/arch/spr_def.h> - - -/* - * In addition to including the proper base SPR definition file, depending - * on machine architecture, this file defines several macros which allow - * kernel code to use protection-level dependent SPRs without worrying - * about which PL it's running at. In these macros, the PL that the SPR - * or interrupt number applies to is replaced by K. - */ - -#if CONFIG_KERNEL_PL != 1 && CONFIG_KERNEL_PL != 2 -#error CONFIG_KERNEL_PL must be 1 or 2 -#endif - -/* Concatenate 4 strings. */ -#define __concat4(a, b, c, d) a ## b ## c ## d -#define _concat4(a, b, c, d) __concat4(a, b, c, d) - -#ifdef __tilegx__ - -/* TILE-Gx dependent, protection-level dependent SPRs. */ - -#define SPR_INTERRUPT_MASK_K \ - _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL,,) -#define SPR_INTERRUPT_MASK_SET_K \ - _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL,,) -#define SPR_INTERRUPT_MASK_RESET_K \ - _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL,,) -#define SPR_INTERRUPT_VECTOR_BASE_K \ - _concat4(SPR_INTERRUPT_VECTOR_BASE_, CONFIG_KERNEL_PL,,) - -#define SPR_IPI_MASK_K \ - _concat4(SPR_IPI_MASK_, CONFIG_KERNEL_PL,,) -#define SPR_IPI_MASK_RESET_K \ - _concat4(SPR_IPI_MASK_RESET_, CONFIG_KERNEL_PL,,) -#define SPR_IPI_MASK_SET_K \ - _concat4(SPR_IPI_MASK_SET_, CONFIG_KERNEL_PL,,) -#define SPR_IPI_EVENT_K \ - _concat4(SPR_IPI_EVENT_, CONFIG_KERNEL_PL,,) -#define SPR_IPI_EVENT_RESET_K \ - _concat4(SPR_IPI_EVENT_RESET_, CONFIG_KERNEL_PL,,) -#define SPR_IPI_EVENT_SET_K \ - _concat4(SPR_IPI_EVENT_SET_, CONFIG_KERNEL_PL,,) -#define INT_IPI_K \ - _concat4(INT_IPI_, CONFIG_KERNEL_PL,,) - -#define SPR_SINGLE_STEP_CONTROL_K \ - _concat4(SPR_SINGLE_STEP_CONTROL_, CONFIG_KERNEL_PL,,) -#define SPR_SINGLE_STEP_EN_K_K \ - _concat4(SPR_SINGLE_STEP_EN_, CONFIG_KERNEL_PL, _, CONFIG_KERNEL_PL) -#define INT_SINGLE_STEP_K \ - _concat4(INT_SINGLE_STEP_, CONFIG_KERNEL_PL,,) - -#else - -/* TILEPro dependent, protection-level dependent SPRs. */ - -#define SPR_INTERRUPT_MASK_K_0 \ - _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _0,) -#define SPR_INTERRUPT_MASK_K_1 \ - _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _1,) -#define SPR_INTERRUPT_MASK_SET_K_0 \ - _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _0,) -#define SPR_INTERRUPT_MASK_SET_K_1 \ - _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _1,) -#define SPR_INTERRUPT_MASK_RESET_K_0 \ - _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _0,) -#define SPR_INTERRUPT_MASK_RESET_K_1 \ - _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _1,) - -#endif - -/* Generic protection-level dependent SPRs. */ - -#define SPR_SYSTEM_SAVE_K_0 \ - _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _0,) -#define SPR_SYSTEM_SAVE_K_1 \ - _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _1,) -#define SPR_SYSTEM_SAVE_K_2 \ - _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _2,) -#define SPR_SYSTEM_SAVE_K_3 \ - _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _3,) -#define SPR_EX_CONTEXT_K_0 \ - _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _0,) -#define SPR_EX_CONTEXT_K_1 \ - _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _1,) -#define SPR_INTCTRL_K_STATUS \ - _concat4(SPR_INTCTRL_, CONFIG_KERNEL_PL, _STATUS,) -#define INT_INTCTRL_K \ - _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,) - -#endif /* __ARCH_SPR_DEF_H__ */ diff --git a/arch/tile/include/arch/trio.h b/arch/tile/include/arch/trio.h deleted file mode 100644 index c0ddedcae085..000000000000 --- a/arch/tile/include/arch/trio.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_H__ -#define __ARCH_TRIO_H__ - -#include <arch/abi.h> -#include <arch/trio_def.h> - -#ifndef __ASSEMBLER__ - -/* - * Map SQ Doorbell Format. - * This describes the format of the write-only doorbell register that exists - * in the last 8-bytes of the MAP_SQ_BASE/LIM range. This register is only - * writable from PCIe space. Writes to this register will not be written to - * Tile memory space and thus no IO VA translation is required if the last - * page of the BASE/LIM range is not otherwise written. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * When written with a 1, the associated MAP_SQ region's doorbell - * interrupt will be triggered once all previous writes are visible to - * Tile software. - */ - uint_reg_t doorbell : 1; - /* - * When written with a 1, the descriptor at the head of the associated - * MAP_SQ's FIFO will be dequeued. - */ - uint_reg_t pop : 1; - /* Reserved. */ - uint_reg_t __reserved : 62; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved : 62; - uint_reg_t pop : 1; - uint_reg_t doorbell : 1; -#endif - }; - - uint_reg_t word; -} TRIO_MAP_SQ_DOORBELL_FMT_t; - - -/* - * Tile PIO Region Configuration - CFG Address Format. - * This register describes the address format for PIO accesses when the - * associated region is setup with TYPE=CFG. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Register Address (full byte address). */ - uint_reg_t reg_addr : 12; - /* Function Number */ - uint_reg_t fn : 3; - /* Device Number */ - uint_reg_t dev : 5; - /* BUS Number */ - uint_reg_t bus : 8; - /* Config Type: 0 for access to directly-attached device. 1 otherwise. */ - uint_reg_t type : 1; - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* - * MAC select. This must match the configuration in - * TILE_PIO_REGION_SETUP.MAC. - */ - uint_reg_t mac : 2; - /* Reserved. */ - uint_reg_t __reserved_1 : 32; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_1 : 32; - uint_reg_t mac : 2; - uint_reg_t __reserved_0 : 1; - uint_reg_t type : 1; - uint_reg_t bus : 8; - uint_reg_t dev : 5; - uint_reg_t fn : 3; - uint_reg_t reg_addr : 12; -#endif - }; - - uint_reg_t word; -} TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_TRIO_H__) */ diff --git a/arch/tile/include/arch/trio_constants.h b/arch/tile/include/arch/trio_constants.h deleted file mode 100644 index 85647e91a458..000000000000 --- a/arch/tile/include/arch/trio_constants.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - - -#ifndef __ARCH_TRIO_CONSTANTS_H__ -#define __ARCH_TRIO_CONSTANTS_H__ - -#define TRIO_NUM_ASIDS 32 -#define TRIO_NUM_TLBS_PER_ASID 16 - -#define TRIO_NUM_TPIO_REGIONS 8 -#define TRIO_LOG2_NUM_TPIO_REGIONS 3 - -#define TRIO_NUM_MAP_MEM_REGIONS 32 -#define TRIO_LOG2_NUM_MAP_MEM_REGIONS 5 -#define TRIO_NUM_MAP_SQ_REGIONS 8 -#define TRIO_LOG2_NUM_MAP_SQ_REGIONS 3 - -#define TRIO_LOG2_NUM_SQ_FIFO_ENTRIES 6 - -#define TRIO_NUM_PUSH_DMA_RINGS 64 - -#define TRIO_NUM_PULL_DMA_RINGS 64 - -#endif /* __ARCH_TRIO_CONSTANTS_H__ */ diff --git a/arch/tile/include/arch/trio_def.h b/arch/tile/include/arch/trio_def.h deleted file mode 100644 index e80500317dc4..000000000000 --- a/arch/tile/include/arch/trio_def.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_DEF_H__ -#define __ARCH_TRIO_DEF_H__ -#define TRIO_CFG_REGION_ADDR__REG_SHIFT 0 -#define TRIO_CFG_REGION_ADDR__INTFC_SHIFT 16 -#define TRIO_CFG_REGION_ADDR__INTFC_VAL_TRIO 0x0 -#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE 0x1 -#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD 0x2 -#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 0x3 -#define TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT 18 -#define TRIO_CFG_REGION_ADDR__PROT_SHIFT 20 -#define TRIO_PIO_REGIONS_ADDR__REGION_SHIFT 32 -#define TRIO_MAP_MEM_REG_INT0 0x1000000000 -#define TRIO_MAP_MEM_REG_INT1 0x1000000008 -#define TRIO_MAP_MEM_REG_INT2 0x1000000010 -#define TRIO_MAP_MEM_REG_INT3 0x1000000018 -#define TRIO_MAP_MEM_REG_INT4 0x1000000020 -#define TRIO_MAP_MEM_REG_INT5 0x1000000028 -#define TRIO_MAP_MEM_REG_INT6 0x1000000030 -#define TRIO_MAP_MEM_REG_INT7 0x1000000038 -#define TRIO_MAP_MEM_LIM__ADDR_SHIFT 12 -#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED 0x0 -#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT 0x1 -#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD 0x2 -#define TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT 30 -#endif /* !defined(__ARCH_TRIO_DEF_H__) */ diff --git a/arch/tile/include/arch/trio_pcie_intfc.h b/arch/tile/include/arch/trio_pcie_intfc.h deleted file mode 100644 index 0487fdb9d581..000000000000 --- a/arch/tile/include/arch/trio_pcie_intfc.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_PCIE_INTFC_H__ -#define __ARCH_TRIO_PCIE_INTFC_H__ - -#include <arch/abi.h> -#include <arch/trio_pcie_intfc_def.h> - -#ifndef __ASSEMBLER__ - -/* - * Port Configuration. - * Configuration of the PCIe Port - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Provides the state of the strapping pins for this port. */ - uint_reg_t strap_state : 3; - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* - * When 1, the device type will be overridden using OVD_DEV_TYPE_VAL. - * When 0, the device type is determined based on the STRAP_STATE. - */ - uint_reg_t ovd_dev_type : 1; - /* Provides the device type when OVD_DEV_TYPE is 1. */ - uint_reg_t ovd_dev_type_val : 4; - /* Determines how link is trained. */ - uint_reg_t train_mode : 2; - /* Reserved. */ - uint_reg_t __reserved_1 : 1; - /* - * For PCIe, used to flip physical RX lanes that were not properly wired. - * This is not the same as lane reversal which is handled automatically - * during link training. When 0, RX Lane0 must be wired to the link - * partner (either to its Lane0 or it's LaneN). When RX_LANE_FLIP is 1, - * the highest numbered lane for this port becomes Lane0 and Lane0 does - * NOT have to be wired to the link partner. - */ - uint_reg_t rx_lane_flip : 1; - /* - * For PCIe, used to flip physical TX lanes that were not properly wired. - * This is not the same as lane reversal which is handled automatically - * during link training. When 0, TX Lane0 must be wired to the link - * partner (either to its Lane0 or it's LaneN). When TX_LANE_FLIP is 1, - * the highest numbered lane for this port becomes Lane0 and Lane0 does - * NOT have to be wired to the link partner. - */ - uint_reg_t tx_lane_flip : 1; - /* - * For StreamIO port, configures the width of the port when TRAIN_MODE is - * not STRAP. - */ - uint_reg_t stream_width : 2; - /* - * For StreamIO port, configures the rate of the port when TRAIN_MODE is - * not STRAP. - */ - uint_reg_t stream_rate : 2; - /* Reserved. */ - uint_reg_t __reserved_2 : 46; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_2 : 46; - uint_reg_t stream_rate : 2; - uint_reg_t stream_width : 2; - uint_reg_t tx_lane_flip : 1; - uint_reg_t rx_lane_flip : 1; - uint_reg_t __reserved_1 : 1; - uint_reg_t train_mode : 2; - uint_reg_t ovd_dev_type_val : 4; - uint_reg_t ovd_dev_type : 1; - uint_reg_t __reserved_0 : 1; - uint_reg_t strap_state : 3; -#endif - }; - - uint_reg_t word; -} TRIO_PCIE_INTFC_PORT_CONFIG_t; - -/* - * Port Status. - * Status of the PCIe Port. This register applies to the StreamIO port when - * StreamIO is enabled. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * Indicates the DL state of the port. When 1, the port is up and ready - * to receive traffic. - */ - uint_reg_t dl_up : 1; - /* - * Indicates the number of times the link has gone down. Clears on read. - */ - uint_reg_t dl_down_cnt : 7; - /* Indicates the SERDES PLL has spun up and is providing a valid clock. */ - uint_reg_t clock_ready : 1; - /* Reserved. */ - uint_reg_t __reserved_0 : 7; - /* Device revision ID. */ - uint_reg_t device_rev : 8; - /* Link state (PCIe). */ - uint_reg_t ltssm_state : 6; - /* Link power management state (PCIe). */ - uint_reg_t pm_state : 3; - /* Reserved. */ - uint_reg_t __reserved_1 : 31; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_1 : 31; - uint_reg_t pm_state : 3; - uint_reg_t ltssm_state : 6; - uint_reg_t device_rev : 8; - uint_reg_t __reserved_0 : 7; - uint_reg_t clock_ready : 1; - uint_reg_t dl_down_cnt : 7; - uint_reg_t dl_up : 1; -#endif - }; - - uint_reg_t word; -} TRIO_PCIE_INTFC_PORT_STATUS_t; - -/* - * Transmit FIFO Control. - * Contains TX FIFO thresholds. These registers are for diagnostics purposes - * only. Changing these values causes undefined behavior. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * Almost-Empty level for TX0 data. Typically set to at least - * roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz - * for a x4 port (250MHz). - */ - uint_reg_t tx0_data_ae_lvl : 7; - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* Almost-Empty level for TX1 data. */ - uint_reg_t tx1_data_ae_lvl : 7; - /* Reserved. */ - uint_reg_t __reserved_1 : 1; - /* Almost-Full level for TX0 data. */ - uint_reg_t tx0_data_af_lvl : 7; - /* Reserved. */ - uint_reg_t __reserved_2 : 1; - /* Almost-Full level for TX1 data. */ - uint_reg_t tx1_data_af_lvl : 7; - /* Reserved. */ - uint_reg_t __reserved_3 : 1; - /* Almost-Full level for TX0 info. */ - uint_reg_t tx0_info_af_lvl : 5; - /* Reserved. */ - uint_reg_t __reserved_4 : 3; - /* Almost-Full level for TX1 info. */ - uint_reg_t tx1_info_af_lvl : 5; - /* Reserved. */ - uint_reg_t __reserved_5 : 3; - /* - * This register provides performance adjustment for high bandwidth - * flows. The MAC will assert almost-full to TRIO if non-posted credits - * fall below this level. Note that setting this larger than the initial - * PORT_CREDIT.NPH value will cause READS to never be sent. If the - * initial credit value from the link partner is smaller than this value - * when the link comes up, the value will be reset to the initial credit - * value to prevent lockup. - */ - uint_reg_t min_np_credits : 8; - /* - * This register provides performance adjustment for high bandwidth - * flows. The MAC will assert almost-full to TRIO if posted credits fall - * below this level. Note that setting this larger than the initial - * PORT_CREDIT.PH value will cause WRITES to never be sent. If the - * initial credit value from the link partner is smaller than this value - * when the link comes up, the value will be reset to the initial credit - * value to prevent lockup. - */ - uint_reg_t min_p_credits : 8; -#else /* __BIG_ENDIAN__ */ - uint_reg_t min_p_credits : 8; - uint_reg_t min_np_credits : 8; - uint_reg_t __reserved_5 : 3; - uint_reg_t tx1_info_af_lvl : 5; - uint_reg_t __reserved_4 : 3; - uint_reg_t tx0_info_af_lvl : 5; - uint_reg_t __reserved_3 : 1; - uint_reg_t tx1_data_af_lvl : 7; - uint_reg_t __reserved_2 : 1; - uint_reg_t tx0_data_af_lvl : 7; - uint_reg_t __reserved_1 : 1; - uint_reg_t tx1_data_ae_lvl : 7; - uint_reg_t __reserved_0 : 1; - uint_reg_t tx0_data_ae_lvl : 7; -#endif - }; - - uint_reg_t word; -} TRIO_PCIE_INTFC_TX_FIFO_CTL_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */ diff --git a/arch/tile/include/arch/trio_pcie_intfc_def.h b/arch/tile/include/arch/trio_pcie_intfc_def.h deleted file mode 100644 index d3fd6781fb24..000000000000 --- a/arch/tile/include/arch/trio_pcie_intfc_def.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_PCIE_INTFC_DEF_H__ -#define __ARCH_TRIO_PCIE_INTFC_DEF_H__ -#define TRIO_PCIE_INTFC_MAC_INT_STS 0x0000 -#define TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK 0xf000 -#define TRIO_PCIE_INTFC_PORT_CONFIG 0x0018 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_DISABLED 0x0 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT 0x1 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC 0x2 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 0x3 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1 0x4 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_XLINK 0x5 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X1 0x6 -#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X4 0x7 -#define TRIO_PCIE_INTFC_PORT_STATUS 0x0020 -#define TRIO_PCIE_INTFC_TX_FIFO_CTL 0x0050 -#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_DEF_H__) */ diff --git a/arch/tile/include/arch/trio_pcie_rc.h b/arch/tile/include/arch/trio_pcie_rc.h deleted file mode 100644 index 6a25d0aca857..000000000000 --- a/arch/tile/include/arch/trio_pcie_rc.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_PCIE_RC_H__ -#define __ARCH_TRIO_PCIE_RC_H__ - -#include <arch/abi.h> -#include <arch/trio_pcie_rc_def.h> - -#ifndef __ASSEMBLER__ - -/* Device Capabilities Register. */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * Max_Payload_Size Supported, writablethrough the MAC_STANDARD interface - */ - uint_reg_t mps_sup : 3; - /* - * This field is writable through the MAC_STANDARD interface. However, - * Phantom Function is not supported. Therefore, the application must - * not write any value other than 0x0 to this field. - */ - uint_reg_t phantom_function_supported : 2; - /* This bit is writable through the MAC_STANDARD interface. */ - uint_reg_t ext_tag_field_supported : 1; - /* Reserved. */ - uint_reg_t __reserved_0 : 3; - /* Endpoint L1 Acceptable Latency Must be 0x0 for non-Endpoint devices. */ - uint_reg_t l1_lat : 3; - /* - * Undefined since PCI Express 1.1 (Was Attention Button Present for PCI - * Express 1.0a) - */ - uint_reg_t r1 : 1; - /* - * Undefined since PCI Express 1.1 (Was Attention Indicator Present for - * PCI Express 1.0a) - */ - uint_reg_t r2 : 1; - /* - * Undefined since PCI Express 1.1 (Was Power Indicator Present for PCI - * Express 1.0a) - */ - uint_reg_t r3 : 1; - /* - * Role-Based Error Reporting, writable through the MAC_STANDARD - * interface. Required to be set for device compliant to 1.1 spec and - * later. - */ - uint_reg_t rer : 1; - /* Reserved. */ - uint_reg_t __reserved_1 : 2; - /* Captured Slot Power Limit Value Upstream port only. */ - uint_reg_t slot_pwr_lim : 8; - /* Captured Slot Power Limit Scale Upstream port only. */ - uint_reg_t slot_pwr_scale : 2; - /* Reserved. */ - uint_reg_t __reserved_2 : 4; - /* Endpoint L0s Acceptable LatencyMust be 0x0 for non-Endpoint devices. */ - uint_reg_t l0s_lat : 1; - /* Reserved. */ - uint_reg_t __reserved_3 : 31; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_3 : 31; - uint_reg_t l0s_lat : 1; - uint_reg_t __reserved_2 : 4; - uint_reg_t slot_pwr_scale : 2; - uint_reg_t slot_pwr_lim : 8; - uint_reg_t __reserved_1 : 2; - uint_reg_t rer : 1; - uint_reg_t r3 : 1; - uint_reg_t r2 : 1; - uint_reg_t r1 : 1; - uint_reg_t l1_lat : 3; - uint_reg_t __reserved_0 : 3; - uint_reg_t ext_tag_field_supported : 1; - uint_reg_t phantom_function_supported : 2; - uint_reg_t mps_sup : 3; -#endif - }; - - uint_reg_t word; -} TRIO_PCIE_RC_DEVICE_CAP_t; - -/* Device Control Register. */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Correctable Error Reporting Enable */ - uint_reg_t cor_err_ena : 1; - /* Non-Fatal Error Reporting Enable */ - uint_reg_t nf_err_ena : 1; - /* Fatal Error Reporting Enable */ - uint_reg_t fatal_err_ena : 1; - /* Unsupported Request Reporting Enable */ - uint_reg_t ur_ena : 1; - /* Relaxed orderring enable */ - uint_reg_t ro_ena : 1; - /* Max Payload Size */ - uint_reg_t max_payload_size : 3; - /* Extended Tag Field Enable */ - uint_reg_t ext_tag : 1; - /* Phantom Function Enable */ - uint_reg_t ph_fn_ena : 1; - /* AUX Power PM Enable */ - uint_reg_t aux_pm_ena : 1; - /* Enable NoSnoop */ - uint_reg_t no_snoop : 1; - /* Max read request size */ - uint_reg_t max_read_req_sz : 3; - /* Reserved. */ - uint_reg_t __reserved : 49; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved : 49; - uint_reg_t max_read_req_sz : 3; - uint_reg_t no_snoop : 1; - uint_reg_t aux_pm_ena : 1; - uint_reg_t ph_fn_ena : 1; - uint_reg_t ext_tag : 1; - uint_reg_t max_payload_size : 3; - uint_reg_t ro_ena : 1; - uint_reg_t ur_ena : 1; - uint_reg_t fatal_err_ena : 1; - uint_reg_t nf_err_ena : 1; - uint_reg_t cor_err_ena : 1; -#endif - }; - - uint_reg_t word; -} TRIO_PCIE_RC_DEVICE_CONTROL_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_TRIO_PCIE_RC_H__) */ diff --git a/arch/tile/include/arch/trio_pcie_rc_def.h b/arch/tile/include/arch/trio_pcie_rc_def.h deleted file mode 100644 index 74081a65b6f2..000000000000 --- a/arch/tile/include/arch/trio_pcie_rc_def.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_PCIE_RC_DEF_H__ -#define __ARCH_TRIO_PCIE_RC_DEF_H__ -#define TRIO_PCIE_RC_DEVICE_CAP 0x0074 -#define TRIO_PCIE_RC_DEVICE_CONTROL 0x0078 -#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID 0x0000 -#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT 16 -#define TRIO_PCIE_RC_REVISION_ID 0x0008 -#endif /* !defined(__ARCH_TRIO_PCIE_RC_DEF_H__) */ diff --git a/arch/tile/include/arch/trio_shm.h b/arch/tile/include/arch/trio_shm.h deleted file mode 100644 index 3382e38245af..000000000000 --- a/arch/tile/include/arch/trio_shm.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - - -#ifndef __ARCH_TRIO_SHM_H__ -#define __ARCH_TRIO_SHM_H__ - -#include <arch/abi.h> -#include <arch/trio_shm_def.h> - -#ifndef __ASSEMBLER__ -/** - * TRIO DMA Descriptor. - * The TRIO DMA descriptor is written by software and consumed by hardware. - * It is used to specify the location of transaction data in the IO and Tile - * domains. - */ - -__extension__ -typedef union -{ - struct - { - /* Word 0 */ - -#ifndef __BIG_ENDIAN__ - /** Tile side virtual address. */ - int_reg_t va : 42; - /** - * Encoded size of buffer used on push DMA when C=1: - * 0 = 128 bytes - * 1 = 256 bytes - * 2 = 512 bytes - * 3 = 1024 bytes - * 4 = 1664 bytes - * 5 = 4096 bytes - * 6 = 10368 bytes - * 7 = 16384 bytes - */ - uint_reg_t bsz : 3; - /** - * Chaining designation. Always zero for pull DMA - * 0 : Unchained buffer pointer - * 1 : Chained buffer pointer. Next buffer descriptor (e.g. VA) stored - * in 1st 8-bytes in buffer. For chained buffers, first 8-bytes of each - * buffer contain the next buffer descriptor formatted exactly like a PDE - * buffer descriptor. This allows a chained PDE buffer to be sent using - * push DMA. - */ - uint_reg_t c : 1; - /** - * Notification interrupt will be delivered when the transaction has - * completed (all data has been read from or written to the Tile-side - * buffer). - */ - uint_reg_t notif : 1; - /** - * When 0, the XSIZE field specifies the total byte count for the - * transaction. When 1, the XSIZE field is encoded as 2^(N+14) for N in - * {0..6}: - * 0 = 16KB - * 1 = 32KB - * 2 = 64KB - * 3 = 128KB - * 4 = 256KB - * 5 = 512KB - * 6 = 1MB - * All other encodings of the XSIZE field are reserved when SMOD=1 - */ - uint_reg_t smod : 1; - /** - * Total number of bytes to move for this transaction. When SMOD=1, - * this field is encoded - see SMOD description. - */ - uint_reg_t xsize : 14; - /** Reserved. */ - uint_reg_t __reserved_0 : 1; - /** - * Generation number. Used to indicate a valid descriptor in ring. When - * a new descriptor is written into the ring, software must toggle this - * bit. The net effect is that the GEN bit being written into new - * descriptors toggles each time the ring tail pointer wraps. - */ - uint_reg_t gen : 1; -#else /* __BIG_ENDIAN__ */ - uint_reg_t gen : 1; - uint_reg_t __reserved_0 : 1; - uint_reg_t xsize : 14; - uint_reg_t smod : 1; - uint_reg_t notif : 1; - uint_reg_t c : 1; - uint_reg_t bsz : 3; - int_reg_t va : 42; -#endif - - /* Word 1 */ - -#ifndef __BIG_ENDIAN__ - /** IO-side address */ - uint_reg_t io_address : 64; -#else /* __BIG_ENDIAN__ */ - uint_reg_t io_address : 64; -#endif - - }; - - /** Word access */ - uint_reg_t words[2]; -} TRIO_DMA_DESC_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_TRIO_SHM_H__) */ diff --git a/arch/tile/include/arch/trio_shm_def.h b/arch/tile/include/arch/trio_shm_def.h deleted file mode 100644 index 72a59c88b06a..000000000000 --- a/arch/tile/include/arch/trio_shm_def.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_TRIO_SHM_DEF_H__ -#define __ARCH_TRIO_SHM_DEF_H__ -#endif /* !defined(__ARCH_TRIO_SHM_DEF_H__) */ diff --git a/arch/tile/include/arch/uart.h b/arch/tile/include/arch/uart.h deleted file mode 100644 index 07966970adad..000000000000 --- a/arch/tile/include/arch/uart.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright 2013 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_UART_H__ -#define __ARCH_UART_H__ - -#include <arch/abi.h> -#include <arch/uart_def.h> - -#ifndef __ASSEMBLER__ - -/* Divisor. */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * Baud Rate Divisor. Desired_baud_rate = REF_CLK frequency / (baud * - * 16). - * Note: REF_CLK is always 125 MHz, the default - * divisor = 68, baud rate = 125M/(68*16) = 115200 baud. - */ - uint_reg_t divisor : 12; - /* Reserved. */ - uint_reg_t __reserved : 52; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved : 52; - uint_reg_t divisor : 12; -#endif - }; - - uint_reg_t word; -} UART_DIVISOR_t; - -/* FIFO Count. */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* - * n: n active entries in the receive FIFO (max is 2**8). Each entry has - * 8 bits. - * 0: no active entry in the receive FIFO (that is empty). - */ - uint_reg_t rfifo_count : 9; - /* Reserved. */ - uint_reg_t __reserved_0 : 7; - /* - * n: n active entries in the transmit FIFO (max is 2**8). Each entry has - * 8 bits. - * 0: no active entry in the transmit FIFO (that is empty). - */ - uint_reg_t tfifo_count : 9; - /* Reserved. */ - uint_reg_t __reserved_1 : 7; - /* - * n: n active entries in the write FIFO (max is 2**2). Each entry has 8 - * bits. - * 0: no active entry in the write FIFO (that is empty). - */ - uint_reg_t wfifo_count : 3; - /* Reserved. */ - uint_reg_t __reserved_2 : 29; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_2 : 29; - uint_reg_t wfifo_count : 3; - uint_reg_t __reserved_1 : 7; - uint_reg_t tfifo_count : 9; - uint_reg_t __reserved_0 : 7; - uint_reg_t rfifo_count : 9; -#endif - }; - - uint_reg_t word; -} UART_FIFO_COUNT_t; - -/* FLAG. */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* 1: receive FIFO is empty */ - uint_reg_t rfifo_empty : 1; - /* 1: write FIFO is empty. */ - uint_reg_t wfifo_empty : 1; - /* 1: transmit FIFO is empty. */ - uint_reg_t tfifo_empty : 1; - /* 1: receive FIFO is full. */ - uint_reg_t rfifo_full : 1; - /* 1: write FIFO is full. */ - uint_reg_t wfifo_full : 1; - /* 1: transmit FIFO is full. */ - uint_reg_t tfifo_full : 1; - /* Reserved. */ - uint_reg_t __reserved_1 : 57; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_1 : 57; - uint_reg_t tfifo_full : 1; - uint_reg_t wfifo_full : 1; - uint_reg_t rfifo_full : 1; - uint_reg_t tfifo_empty : 1; - uint_reg_t wfifo_empty : 1; - uint_reg_t rfifo_empty : 1; - uint_reg_t __reserved_0 : 1; -#endif - }; - - uint_reg_t word; -} UART_FLAG_t; - -/* - * Interrupt Vector Mask. - * Each bit in this register corresponds to a specific interrupt. When set, - * the associated interrupt will not be dispatched. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Read data FIFO read and no data available */ - uint_reg_t rdat_err : 1; - /* Write FIFO was written but it was full */ - uint_reg_t wdat_err : 1; - /* Stop bit not found when current data was received */ - uint_reg_t frame_err : 1; - /* Parity error was detected when current data was received */ - uint_reg_t parity_err : 1; - /* Data was received but the receive FIFO was full */ - uint_reg_t rfifo_overflow : 1; - /* - * An almost full event is reached when data is to be written to the - * receive FIFO, and the receive FIFO has more than or equal to - * BUFFER_THRESHOLD.RFIFO_AFULL bytes. - */ - uint_reg_t rfifo_afull : 1; - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* An entry in the transmit FIFO was popped */ - uint_reg_t tfifo_re : 1; - /* An entry has been pushed into the receive FIFO */ - uint_reg_t rfifo_we : 1; - /* An entry of the write FIFO has been popped */ - uint_reg_t wfifo_re : 1; - /* Rshim read receive FIFO in protocol mode */ - uint_reg_t rfifo_err : 1; - /* - * An almost empty event is reached when data is to be read from the - * transmit FIFO, and the transmit FIFO has less than or equal to - * BUFFER_THRESHOLD.TFIFO_AEMPTY bytes. - */ - uint_reg_t tfifo_aempty : 1; - /* Reserved. */ - uint_reg_t __reserved_1 : 52; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_1 : 52; - uint_reg_t tfifo_aempty : 1; - uint_reg_t rfifo_err : 1; - uint_reg_t wfifo_re : 1; - uint_reg_t rfifo_we : 1; - uint_reg_t tfifo_re : 1; - uint_reg_t __reserved_0 : 1; - uint_reg_t rfifo_afull : 1; - uint_reg_t rfifo_overflow : 1; - uint_reg_t parity_err : 1; - uint_reg_t frame_err : 1; - uint_reg_t wdat_err : 1; - uint_reg_t rdat_err : 1; -#endif - }; - - uint_reg_t word; -} UART_INTERRUPT_MASK_t; - -/* - * Interrupt vector, write-one-to-clear. - * Each bit in this register corresponds to a specific interrupt. Hardware - * sets the bit when the associated condition has occurred. Writing a 1 - * clears the status bit. - */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Read data FIFO read and no data available */ - uint_reg_t rdat_err : 1; - /* Write FIFO was written but it was full */ - uint_reg_t wdat_err : 1; - /* Stop bit not found when current data was received */ - uint_reg_t frame_err : 1; - /* Parity error was detected when current data was received */ - uint_reg_t parity_err : 1; - /* Data was received but the receive FIFO was full */ - uint_reg_t rfifo_overflow : 1; - /* - * Data was received and the receive FIFO is now almost full (more than - * BUFFER_THRESHOLD.RFIFO_AFULL bytes in it) - */ - uint_reg_t rfifo_afull : 1; - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* An entry in the transmit FIFO was popped */ - uint_reg_t tfifo_re : 1; - /* An entry has been pushed into the receive FIFO */ - uint_reg_t rfifo_we : 1; - /* An entry of the write FIFO has been popped */ - uint_reg_t wfifo_re : 1; - /* Rshim read receive FIFO in protocol mode */ - uint_reg_t rfifo_err : 1; - /* - * Data was read from the transmit FIFO and now it is almost empty (less - * than or equal to BUFFER_THRESHOLD.TFIFO_AEMPTY bytes in it). - */ - uint_reg_t tfifo_aempty : 1; - /* Reserved. */ - uint_reg_t __reserved_1 : 52; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_1 : 52; - uint_reg_t tfifo_aempty : 1; - uint_reg_t rfifo_err : 1; - uint_reg_t wfifo_re : 1; - uint_reg_t rfifo_we : 1; - uint_reg_t tfifo_re : 1; - uint_reg_t __reserved_0 : 1; - uint_reg_t rfifo_afull : 1; - uint_reg_t rfifo_overflow : 1; - uint_reg_t parity_err : 1; - uint_reg_t frame_err : 1; - uint_reg_t wdat_err : 1; - uint_reg_t rdat_err : 1; -#endif - }; - - uint_reg_t word; -} UART_INTERRUPT_STATUS_t; - -/* Type. */ - -__extension__ -typedef union -{ - struct - { -#ifndef __BIG_ENDIAN__ - /* Number of stop bits, rx and tx */ - uint_reg_t sbits : 1; - /* Reserved. */ - uint_reg_t __reserved_0 : 1; - /* Data word size, rx and tx */ - uint_reg_t dbits : 1; - /* Reserved. */ - uint_reg_t __reserved_1 : 1; - /* Parity selection, rx and tx */ - uint_reg_t ptype : 3; - /* Reserved. */ - uint_reg_t __reserved_2 : 57; -#else /* __BIG_ENDIAN__ */ - uint_reg_t __reserved_2 : 57; - uint_reg_t ptype : 3; - uint_reg_t __reserved_1 : 1; - uint_reg_t dbits : 1; - uint_reg_t __reserved_0 : 1; - uint_reg_t sbits : 1; -#endif - }; - - uint_reg_t word; -} UART_TYPE_t; -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_UART_H__) */ diff --git a/arch/tile/include/arch/uart_def.h b/arch/tile/include/arch/uart_def.h deleted file mode 100644 index 42bcaf535379..000000000000 --- a/arch/tile/include/arch/uart_def.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2013 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_UART_DEF_H__ -#define __ARCH_UART_DEF_H__ -#define UART_DIVISOR 0x0158 -#define UART_FIFO_COUNT 0x0110 -#define UART_FLAG 0x0108 -#define UART_INTERRUPT_MASK 0x0208 -#define UART_INTERRUPT_MASK__RDAT_ERR_SHIFT 0 -#define UART_INTERRUPT_MASK__RDAT_ERR_WIDTH 1 -#define UART_INTERRUPT_MASK__RDAT_ERR_RESET_VAL 1 -#define UART_INTERRUPT_MASK__RDAT_ERR_RMASK 0x1 -#define UART_INTERRUPT_MASK__RDAT_ERR_MASK 0x1 -#define UART_INTERRUPT_MASK__RDAT_ERR_FIELD 0,0 -#define UART_INTERRUPT_MASK__WDAT_ERR_SHIFT 1 -#define UART_INTERRUPT_MASK__WDAT_ERR_WIDTH 1 -#define UART_INTERRUPT_MASK__WDAT_ERR_RESET_VAL 1 -#define UART_INTERRUPT_MASK__WDAT_ERR_RMASK 0x1 -#define UART_INTERRUPT_MASK__WDAT_ERR_MASK 0x2 -#define UART_INTERRUPT_MASK__WDAT_ERR_FIELD 1,1 -#define UART_INTERRUPT_MASK__FRAME_ERR_SHIFT 2 -#define UART_INTERRUPT_MASK__FRAME_ERR_WIDTH 1 -#define UART_INTERRUPT_MASK__FRAME_ERR_RESET_VAL 1 -#define UART_INTERRUPT_MASK__FRAME_ERR_RMASK 0x1 -#define UART_INTERRUPT_MASK__FRAME_ERR_MASK 0x4 -#define UART_INTERRUPT_MASK__FRAME_ERR_FIELD 2,2 -#define UART_INTERRUPT_MASK__PARITY_ERR_SHIFT 3 -#define UART_INTERRUPT_MASK__PARITY_ERR_WIDTH 1 -#define UART_INTERRUPT_MASK__PARITY_ERR_RESET_VAL 1 -#define UART_INTERRUPT_MASK__PARITY_ERR_RMASK 0x1 -#define UART_INTERRUPT_MASK__PARITY_ERR_MASK 0x8 -#define UART_INTERRUPT_MASK__PARITY_ERR_FIELD 3,3 -#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_SHIFT 4 -#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_WIDTH 1 -#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RESET_VAL 1 -#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RMASK 0x1 -#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_MASK 0x10 -#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_FIELD 4,4 -#define UART_INTERRUPT_MASK__RFIFO_AFULL_SHIFT 5 -#define UART_INTERRUPT_MASK__RFIFO_AFULL_WIDTH 1 -#define UART_INTERRUPT_MASK__RFIFO_AFULL_RESET_VAL 1 -#define UART_INTERRUPT_MASK__RFIFO_AFULL_RMASK 0x1 -#define UART_INTERRUPT_MASK__RFIFO_AFULL_MASK 0x20 -#define UART_INTERRUPT_MASK__RFIFO_AFULL_FIELD 5,5 -#define UART_INTERRUPT_MASK__TFIFO_RE_SHIFT 7 -#define UART_INTERRUPT_MASK__TFIFO_RE_WIDTH 1 -#define UART_INTERRUPT_MASK__TFIFO_RE_RESET_VAL 1 -#define UART_INTERRUPT_MASK__TFIFO_RE_RMASK 0x1 -#define UART_INTERRUPT_MASK__TFIFO_RE_MASK 0x80 -#define UART_INTERRUPT_MASK__TFIFO_RE_FIELD 7,7 -#define UART_INTERRUPT_MASK__RFIFO_WE_SHIFT 8 -#define UART_INTERRUPT_MASK__RFIFO_WE_WIDTH 1 -#define UART_INTERRUPT_MASK__RFIFO_WE_RESET_VAL 1 -#define UART_INTERRUPT_MASK__RFIFO_WE_RMASK 0x1 -#define UART_INTERRUPT_MASK__RFIFO_WE_MASK 0x100 -#define UART_INTERRUPT_MASK__RFIFO_WE_FIELD 8,8 -#define UART_INTERRUPT_MASK__WFIFO_RE_SHIFT 9 -#define UART_INTERRUPT_MASK__WFIFO_RE_WIDTH 1 -#define UART_INTERRUPT_MASK__WFIFO_RE_RESET_VAL 1 -#define UART_INTERRUPT_MASK__WFIFO_RE_RMASK 0x1 -#define UART_INTERRUPT_MASK__WFIFO_RE_MASK 0x200 -#define UART_INTERRUPT_MASK__WFIFO_RE_FIELD 9,9 -#define UART_INTERRUPT_MASK__RFIFO_ERR_SHIFT 10 -#define UART_INTERRUPT_MASK__RFIFO_ERR_WIDTH 1 -#define UART_INTERRUPT_MASK__RFIFO_ERR_RESET_VAL 1 -#define UART_INTERRUPT_MASK__RFIFO_ERR_RMASK 0x1 -#define UART_INTERRUPT_MASK__RFIFO_ERR_MASK 0x400 -#define UART_INTERRUPT_MASK__RFIFO_ERR_FIELD 10,10 -#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_SHIFT 11 -#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_WIDTH 1 -#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RESET_VAL 1 -#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RMASK 0x1 -#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_MASK 0x800 -#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_FIELD 11,11 -#define UART_INTERRUPT_STATUS 0x0200 -#define UART_RECEIVE_DATA 0x0148 -#define UART_TRANSMIT_DATA 0x0140 -#define UART_TYPE 0x0160 -#define UART_TYPE__SBITS_SHIFT 0 -#define UART_TYPE__SBITS_WIDTH 1 -#define UART_TYPE__SBITS_RESET_VAL 1 -#define UART_TYPE__SBITS_RMASK 0x1 -#define UART_TYPE__SBITS_MASK 0x1 -#define UART_TYPE__SBITS_FIELD 0,0 -#define UART_TYPE__SBITS_VAL_ONE_SBITS 0x0 -#define UART_TYPE__SBITS_VAL_TWO_SBITS 0x1 -#define UART_TYPE__DBITS_SHIFT 2 -#define UART_TYPE__DBITS_WIDTH 1 -#define UART_TYPE__DBITS_RESET_VAL 0 -#define UART_TYPE__DBITS_RMASK 0x1 -#define UART_TYPE__DBITS_MASK 0x4 -#define UART_TYPE__DBITS_FIELD 2,2 -#define UART_TYPE__DBITS_VAL_EIGHT_DBITS 0x0 -#define UART_TYPE__DBITS_VAL_SEVEN_DBITS 0x1 -#define UART_TYPE__PTYPE_SHIFT 4 -#define UART_TYPE__PTYPE_WIDTH 3 -#define UART_TYPE__PTYPE_RESET_VAL 3 -#define UART_TYPE__PTYPE_RMASK 0x7 -#define UART_TYPE__PTYPE_MASK 0x70 -#define UART_TYPE__PTYPE_FIELD 4,6 -#define UART_TYPE__PTYPE_VAL_NONE 0x0 -#define UART_TYPE__PTYPE_VAL_MARK 0x1 -#define UART_TYPE__PTYPE_VAL_SPACE 0x2 -#define UART_TYPE__PTYPE_VAL_EVEN 0x3 -#define UART_TYPE__PTYPE_VAL_ODD 0x4 -#endif /* !defined(__ARCH_UART_DEF_H__) */ diff --git a/arch/tile/include/arch/usb_host.h b/arch/tile/include/arch/usb_host.h deleted file mode 100644 index d09f32683962..000000000000 --- a/arch/tile/include/arch/usb_host.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_USB_HOST_H__ -#define __ARCH_USB_HOST_H__ - -#include <arch/abi.h> -#include <arch/usb_host_def.h> - -#ifndef __ASSEMBLER__ -#endif /* !defined(__ASSEMBLER__) */ - -#endif /* !defined(__ARCH_USB_HOST_H__) */ diff --git a/arch/tile/include/arch/usb_host_def.h b/arch/tile/include/arch/usb_host_def.h deleted file mode 100644 index aeed7753e8e1..000000000000 --- a/arch/tile/include/arch/usb_host_def.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -/* Machine-generated file; do not edit. */ - -#ifndef __ARCH_USB_HOST_DEF_H__ -#define __ARCH_USB_HOST_DEF_H__ -#endif /* !defined(__ARCH_USB_HOST_DEF_H__) */ |