diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json new file mode 100644 index 000000000000..c9259682d39e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json @@ -0,0 +1,22 @@ +[ + { + "ArchStdEvent": "LL_CACHE", + "PublicDescription": "Counts transactions that were returned from outside the core cluster. This event counts transactions for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts transactions for L3 cache." + }, + { + "ArchStdEvent": "LL_CACHE_MISS", + "PublicDescription": "Counts transactions that were returned from outside the core cluster and missed in the last level cache" + }, + { + "ArchStdEvent": "LL_CACHE_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for the L3 cache. This event counts read transactions returned from outside the core if those transactions are either hit in the system level cache or missed in the SLC and are returned from any other external sources." + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster but missed in the system level cache. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for L3 cache. This event counts read transactions returned from outside the core if those transactions are missed in the System level Cache. The data source of the transaction is indicated by a field in the CHI transaction returning to the CPU. This event does not count reads caused by cache maintenance operations." + }, + { + "ArchStdEvent": "LL_CACHE_REFILL", + "PublicDescription": "Counts last level accesses that receive data from outside the last level cache." + } +] |