diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64')
90 files changed, 7104 insertions, 155 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json index 7a2b7b200f14..ac75f12e27bf 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json @@ -9,7 +9,9 @@ "ArchStdEvent": "L1D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L1D_CACHE_INVAL" + "ArchStdEvent": "L1D_CACHE_INVAL", + "Errata": "Errata AC03_CPU_41", + "BriefDescription": "L1D cache invalidate. Impacted by errata -" }, { "ArchStdEvent": "L1D_TLB_REFILL_RD" diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json index 18d1f2f76a23..9fe697d12fe0 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json @@ -78,9 +78,6 @@ "ArchStdEvent": "OP_RETIRED" }, { - "ArchStdEvent": "OP_SPEC" - }, - { "PublicDescription": "Operation speculatively executed, NOP", "EventCode": "0x100", "EventName": "NOP_SPEC", diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json index 0711782bfa6b..13382d29b25f 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json @@ -1,6 +1,8 @@ [ { - "ArchStdEvent": "LD_RETIRED" + "ArchStdEvent": "LD_RETIRED", + "Errata": "Errata AC03_CPU_52", + "BriefDescription": "Instruction architecturally executed, condition code check pass, load. Impacted by errata -" }, { "ArchStdEvent": "MEM_ACCESS_RD" diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json index c50d8e930b05..f4bfe7083a6b 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json @@ -9,7 +9,9 @@ "ArchStdEvent": "L1D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L1D_CACHE_INVAL" + "ArchStdEvent": "L1D_CACHE_INVAL", + "Errata": "Errata AC04_CPU_1", + "BriefDescription": "L1D cache invalidate. Impacted by errata -" }, { "ArchStdEvent": "L1D_TLB_REFILL_RD" diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json index a211d94aacde..6c06bc928415 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json @@ -1,6 +1,8 @@ [ { - "ArchStdEvent": "LD_RETIRED" + "ArchStdEvent": "LD_RETIRED", + "Errata": "Errata AC04_CPU_21", + "BriefDescription": "Instruction architecturally executed, condition code check pass, load. Impacted by errata -" }, { "ArchStdEvent": "MEM_ACCESS_RD" diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json index c5d1d22bd034..5228f94a793f 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json @@ -229,19 +229,19 @@ }, { "MetricName": "slots_lost_misspeculation_fraction", - "MetricExpr": "(OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots)", + "MetricExpr": "100 * (OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots)", "BriefDescription": "Fraction of slots lost due to misspeculation", "DefaultMetricgroupName": "TopdownL1", "MetricGroup": "Default;TopdownL1", - "ScaleUnit": "100percent of slots" + "ScaleUnit": "1percent of slots" }, { "MetricName": "retired_fraction", - "MetricExpr": "OP_RETIRED / (CPU_CYCLES * #slots)", + "MetricExpr": "100 * OP_RETIRED / (CPU_CYCLES * #slots)", "BriefDescription": "Fraction of slots retiring, useful work", "DefaultMetricgroupName": "TopdownL1", "MetricGroup": "Default;TopdownL1", - "ScaleUnit": "100percent of slots" + "ScaleUnit": "1percent of slots" }, { "MetricName": "backend_core", @@ -266,7 +266,7 @@ }, { "MetricName": "frontend_bandwidth", - "MetricExpr": "frontend_bound - frontend_latency", + "MetricExpr": "frontend_bound - 100 * frontend_latency", "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)", "MetricGroup": "TopdownL2", "ScaleUnit": "1percent of slots" diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json index 4404b8e91690..7126fbf292e0 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json @@ -5,7 +5,7 @@ }, { "ArchStdEvent": "EXC_RETURN", - "PublicDescription": "Counts any architecturally executed exception return instructions. Eg: AArch64: ERET" + "PublicDescription": "Counts any architecturally executed exception return instructions. For example: AArch64: ERET" }, { "ArchStdEvent": "EXC_UNDEF", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json index 428810f855b8..c5dcdcf43c58 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json @@ -5,6 +5,6 @@ }, { "ArchStdEvent": "CNT_CYCLES", - "PublicDescription": "Counts constant frequency cycles" + "PublicDescription": "Increments at a constant frequency equal to the rate of increment of the System Counter, CNTPCT_EL0." } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json index da7c129f2569..799d106d5173 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json @@ -1,11 +1,11 @@ [ { "ArchStdEvent": "L1D_CACHE_REFILL", - "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line. This event does not count cache line allocations from preload instructions or from hardware cache prefetching." + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line." }, { "ArchStdEvent": "L1D_CACHE", - "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) count as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." }, { "ArchStdEvent": "L1D_CACHE_WB", @@ -17,7 +17,7 @@ }, { "ArchStdEvent": "L1D_CACHE_RD", - "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches count as both a write access and read access." + "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access." }, { "ArchStdEvent": "L1D_CACHE_WR", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json index 0e31d0daf88b..ed8291ab9737 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json @@ -1,11 +1,11 @@ [ { "ArchStdEvent": "L2D_CACHE", - "PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level caches or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." + "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." }, { "ArchStdEvent": "L2D_CACHE_REFILL", - "PublicDescription": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_WB", @@ -13,23 +13,23 @@ }, { "ArchStdEvent": "L2D_CACHE_ALLOCATE", - "PublicDescription": "TBD" + "PublicDescription": "Counts level 2 cache line allocates that do not fetch data from outside the level 2 data or unified cache." }, { "ArchStdEvent": "L2D_CACHE_RD", - "PublicDescription": "Counts level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_WR", - "PublicDescription": "Counts level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_REFILL_RD", - "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_REFILL_WR", - "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_WB_VICTIM", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json index 45bfba532df7..4a2e72fc5ada 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json @@ -9,11 +9,11 @@ }, { "ArchStdEvent": "L3D_CACHE", - "PublicDescription": "Counts level 3 cache accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." + "PublicDescription": "Counts level 3 cache accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." }, { "ArchStdEvent": "L3D_CACHE_RD", - "PublicDescription": "TBD" + "PublicDescription": "Counts level 3 cache accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." }, { "ArchStdEvent": "L3D_CACHE_LMISS_RD", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json index bb712d57d58a..fd5a2e0099b8 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json @@ -1,10 +1,10 @@ [ { "ArchStdEvent": "LL_CACHE_RD", - "PublicDescription": "Counts read transactions that were returned from outside the core cluster. This event counts when the system register CPUECTLR.EXTLLC bit is set. This event counts read transactions returned from outside the core if those transactions are either hit in the system level cache or missed in the SLC and are returned from any other external sources." + "PublicDescription": "Counts read transactions that were returned from outside the core cluster. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for the L3 cache. This event counts read transactions returned from outside the core if those transactions are either hit in the system level cache or missed in the SLC and are returned from any other external sources." }, { "ArchStdEvent": "LL_CACHE_MISS_RD", - "PublicDescription": "Counts read transactions that were returned from outside the core cluster but missed in the system level cache. This event counts when the system register CPUECTLR.EXTLLC bit is set. This event counts read transactions returned from outside the core if those transactions are missed in the System level Cache. The data source of the transaction is indicated by a field in the CHI transaction returning to the CPU. This event does not count reads caused by cache maintenance operations." + "PublicDescription": "Counts read transactions that were returned from outside the core cluster but missed in the system level cache. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for L3 cache. This event counts read transactions returned from outside the core if those transactions are missed in the System level Cache. The data source of the transaction is indicated by a field in the CHI transaction returning to the CPU. This event does not count reads caused by cache maintenance operations." } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json index 106a97f8b2e7..bb3491012a8f 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json @@ -33,7 +33,7 @@ }, { "ArchStdEvent": "MEM_ACCESS_CHECKED", - "PublicDescription": "Counts the number of memory read and write accesses in a cycle that are tag checked by the Memory Tagging Extension (MTE)." + "PublicDescription": "Counts the number of memory read and write accesses counted by MEM_ACCESS that are tag checked by the Memory Tagging Extension (MTE). This event is implemented as the sum of MEM_ACCESS_CHECKED_RD and MEM_ACCESS_CHECKED_WR" }, { "ArchStdEvent": "MEM_ACCESS_CHECKED_RD", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json index 5f449270b448..97d352f94323 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json @@ -5,7 +5,7 @@ }, { "MetricName": "backend_stalled_cycles", - "MetricExpr": "((STALL_BACKEND / CPU_CYCLES) * 100)", + "MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100", "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.", "MetricGroup": "Cycle_Accounting", "ScaleUnit": "1percent of cycles" @@ -16,45 +16,45 @@ }, { "MetricName": "branch_misprediction_ratio", - "MetricExpr": "(BR_MIS_PRED_RETIRED / BR_RETIRED)", + "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", "BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.", "MetricGroup": "Miss_Ratio;Branch_Effectiveness", - "ScaleUnit": "1per branch" + "ScaleUnit": "100percent of branches" }, { "MetricName": "branch_mpki", - "MetricExpr": "((BR_MIS_PRED_RETIRED / INST_RETIRED) * 1000)", + "MetricExpr": "BR_MIS_PRED_RETIRED / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.", "MetricGroup": "MPKI;Branch_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "branch_percentage", - "MetricExpr": "(((BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC) * 100)", + "MetricExpr": "(BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC * 100", "BriefDescription": "This metric measures branch operations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "crypto_percentage", - "MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)", + "MetricExpr": "CRYPTO_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "dtlb_mpki", - "MetricExpr": "((DTLB_WALK / INST_RETIRED) * 1000)", + "MetricExpr": "DTLB_WALK / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.", "MetricGroup": "MPKI;DTLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "dtlb_walk_ratio", - "MetricExpr": "(DTLB_WALK / L1D_TLB)", + "MetricExpr": "DTLB_WALK / L1D_TLB", "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "ArchStdEvent": "frontend_bound", @@ -62,147 +62,147 @@ }, { "MetricName": "frontend_stalled_cycles", - "MetricExpr": "((STALL_FRONTEND / CPU_CYCLES) * 100)", + "MetricExpr": "STALL_FRONTEND / CPU_CYCLES * 100", "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.", "MetricGroup": "Cycle_Accounting", "ScaleUnit": "1percent of cycles" }, { "MetricName": "integer_dp_percentage", - "MetricExpr": "((DP_SPEC / INST_SPEC) * 100)", + "MetricExpr": "DP_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "ipc", - "MetricExpr": "(INST_RETIRED / CPU_CYCLES)", + "MetricExpr": "INST_RETIRED / CPU_CYCLES", "BriefDescription": "This metric measures the number of instructions retired per cycle.", "MetricGroup": "General", "ScaleUnit": "1per cycle" }, { "MetricName": "itlb_mpki", - "MetricExpr": "((ITLB_WALK / INST_RETIRED) * 1000)", + "MetricExpr": "ITLB_WALK / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.", "MetricGroup": "MPKI;ITLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "itlb_walk_ratio", - "MetricExpr": "(ITLB_WALK / L1I_TLB)", + "MetricExpr": "ITLB_WALK / L1I_TLB", "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l1d_cache_miss_ratio", - "MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)", + "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_mpki", - "MetricExpr": "((L1D_CACHE_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;L1D_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l1d_tlb_miss_ratio", - "MetricExpr": "(L1D_TLB_REFILL / L1D_TLB)", + "MetricExpr": "L1D_TLB_REFILL / L1D_TLB", "BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.", "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l1d_tlb_mpki", - "MetricExpr": "((L1D_TLB_REFILL / INST_RETIRED) * 1000)", - "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", + "MetricExpr": "L1D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;DTLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l1i_cache_miss_ratio", - "MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)", + "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1i_cache_mpki", - "MetricExpr": "((L1I_CACHE_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;L1I_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l1i_tlb_miss_ratio", - "MetricExpr": "(L1I_TLB_REFILL / L1I_TLB)", + "MetricExpr": "L1I_TLB_REFILL / L1I_TLB", "BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.", "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l1i_tlb_mpki", - "MetricExpr": "((L1I_TLB_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L1I_TLB_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;ITLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l2_cache_miss_ratio", - "MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)", + "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l2_cache_mpki", - "MetricExpr": "((L2D_CACHE_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", "MetricGroup": "MPKI;L2_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l2_tlb_miss_ratio", - "MetricExpr": "(L2D_TLB_REFILL / L2D_TLB)", + "MetricExpr": "L2D_TLB_REFILL / L2D_TLB", "BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.", "MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l2_tlb_mpki", - "MetricExpr": "((L2D_TLB_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L2D_TLB_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "ll_cache_read_hit_ratio", - "MetricExpr": "((LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD)", + "MetricExpr": "(LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD", "BriefDescription": "This metric measures the ratio of last level cache read accesses hit in the cache to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", "MetricGroup": "LL_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "ll_cache_read_miss_ratio", - "MetricExpr": "(LL_CACHE_MISS_RD / LL_CACHE_RD)", + "MetricExpr": "LL_CACHE_MISS_RD / LL_CACHE_RD", "BriefDescription": "This metric measures the ratio of last level cache read accesses missed to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", "MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "ll_cache_read_mpki", - "MetricExpr": "((LL_CACHE_MISS_RD / INST_RETIRED) * 1000)", + "MetricExpr": "LL_CACHE_MISS_RD / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of last level cache read accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;LL_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "load_percentage", - "MetricExpr": "((LD_SPEC / INST_SPEC) * 100)", + "MetricExpr": "LD_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" @@ -213,21 +213,21 @@ }, { "MetricName": "scalar_fp_percentage", - "MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)", + "MetricExpr": "VFP_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "simd_percentage", - "MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)", + "MetricExpr": "ASE_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "store_percentage", - "MetricExpr": "((ST_SPEC / INST_SPEC) * 100)", + "MetricExpr": "ST_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" @@ -300,5 +300,12 @@ "MetricGroup": "Operation_Mix", "MetricName": "branch_indirect_spec_rate", "ScaleUnit": "100%" + }, + { + "MetricName": "sve_all_percentage", + "MetricExpr": "SVE_INST_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations, including loads and stores, as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json index f297b049b62f..337e6a916f2b 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json @@ -9,7 +9,7 @@ }, { "ArchStdEvent": "CID_WRITE_RETIRED", - "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR register, which usually contain the kernel PID and can be output with hardware trace." + "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR_EL1 register, which usually contain the kernel PID and can be output with hardware trace." }, { "ArchStdEvent": "TTBR_WRITE_RETIRED", @@ -17,7 +17,7 @@ }, { "ArchStdEvent": "BR_RETIRED", - "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted." + "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted. Note that exception generating instructions, exception return instructions and context synchronization instructions are not counted." }, { "ArchStdEvent": "BR_MIS_PRED_RETIRED", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operation.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operation.json index 1af961f8a6c8..a7ea0d4c4ea4 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operation.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operation.json @@ -5,7 +5,7 @@ }, { "ArchStdEvent": "BR_PRED", - "PublicDescription": "Counts branches speculatively executed and were predicted right." + "PublicDescription": "Counts all speculatively executed branches." }, { "ArchStdEvent": "INST_SPEC", @@ -29,7 +29,7 @@ }, { "ArchStdEvent": "LDREX_SPEC", - "PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: LDREX, LDX" + "PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. For example: LDREX, LDX" }, { "ArchStdEvent": "STREX_PASS_SPEC", @@ -73,15 +73,15 @@ }, { "ArchStdEvent": "BR_IMMED_SPEC", - "PublicDescription": "Counts immediate branch operations which are speculatively executed." + "PublicDescription": "Counts direct branch operations which are speculatively executed." }, { "ArchStdEvent": "BR_RETURN_SPEC", - "PublicDescription": "Counts procedure return operations (RET) which are speculatively executed." + "PublicDescription": "Counts procedure return operations (RET, RETAA and RETAB) which are speculatively executed." }, { "ArchStdEvent": "BR_INDIRECT_SPEC", - "PublicDescription": "Counts indirect branch operations including procedure returns, which are speculatively executed. This includes operations that force a software change of the PC, other than exception-generating operations. Eg: BR Xn, RET" + "PublicDescription": "Counts indirect branch operations including procedure returns, which are speculatively executed. This includes operations that force a software change of the PC, other than exception-generating operations and direct branch instructions. Some examples of the instructions counted by this event include BR Xn, RET, etc..." }, { "ArchStdEvent": "ISB_SPEC", @@ -97,11 +97,11 @@ }, { "ArchStdEvent": "RC_LD_SPEC", - "PublicDescription": "Counts any load acquire operations that are speculatively executed. Eg: LDAR, LDARH, LDARB" + "PublicDescription": "Counts any load acquire operations that are speculatively executed. For example: LDAR, LDARH, LDARB" }, { "ArchStdEvent": "RC_ST_SPEC", - "PublicDescription": "Counts any store release operations that are speculatively executed. Eg: STLR, STLRH, STLRB'" + "PublicDescription": "Counts any store release operations that are speculatively executed. For example: STLR, STLRH, STLRB" }, { "ArchStdEvent": "ASE_INST_SPEC", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json index bbbebc805034..1fcba19dfb7d 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json @@ -1,7 +1,7 @@ [ { "ArchStdEvent": "STALL_FRONTEND", - "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. All the frontend slots were empty during the cycle when this event counts." + "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. STALL_FRONTEND_SLOTS counts SLOTS during the cycle when this event counts." }, { "ArchStdEvent": "STALL_BACKEND", @@ -9,11 +9,11 @@ }, { "ArchStdEvent": "STALL", - "PublicDescription": "Counts cycles when no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall)." + "PublicDescription": "Counts cycles when no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). This event is the sum of STALL_FRONTEND and STALL_BACKEND" }, { "ArchStdEvent": "STALL_SLOT_BACKEND", - "PublicDescription": "Counts slots per cycle in which no operations are sent from the rename unit to the backend due to backend resource constraints." + "PublicDescription": "Counts slots per cycle in which no operations are sent from the rename unit to the backend due to backend resource constraints. STALL_BACKEND counts during the cycle when STALL_SLOT_BACKEND counts at least 1." }, { "ArchStdEvent": "STALL_SLOT_FRONTEND", @@ -21,7 +21,7 @@ }, { "ArchStdEvent": "STALL_SLOT", - "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall)." + "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). STALL_SLOT is the sum of STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND." }, { "ArchStdEvent": "STALL_BACKEND_MEM", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json index b550af1831f5..5704f1e83af9 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json @@ -25,11 +25,11 @@ }, { "ArchStdEvent": "DTLB_WALK", - "PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB driven by a memory access. Note that partial translations that also cause a table walk are counted. This event does not count table walks caused by TLB maintenance operations." + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." }, { "ArchStdEvent": "ITLB_WALK", - "PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. This event does not count table walks caused by TLB maintenance operations." + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." }, { "ArchStdEvent": "L1D_TLB_REFILL_RD", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/bus.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/bus.json new file mode 100644 index 000000000000..2e11a8c4a484 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/bus.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "BUS_ACCESS", + "PublicDescription": "Counts memory transactions issued by the CPU to the external bus, including snoop requests and snoop responses. Each beat of data is counted individually." + }, + { + "ArchStdEvent": "BUS_CYCLES", + "PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES." + }, + { + "ArchStdEvent": "BUS_ACCESS_RD", + "PublicDescription": "Counts memory read transactions seen on the external bus. Each beat of data is counted individually." + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + "PublicDescription": "Counts memory write transactions seen on the external bus. Each beat of data is counted individually." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/exception.json new file mode 100644 index 000000000000..7126fbf292e0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/exception.json @@ -0,0 +1,62 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN", + "PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally." + }, + { + "ArchStdEvent": "EXC_RETURN", + "PublicDescription": "Counts any architecturally executed exception return instructions. For example: AArch64: ERET" + }, + { + "ArchStdEvent": "EXC_UNDEF", + "PublicDescription": "Counts the number of synchronous exceptions which are taken locally that are due to attempting to execute an instruction that is UNDEFINED. Attempting to execute instruction bit patterns that have not been allocated. Attempting to execute instructions when they are disabled. Attempting to execute instructions at an inappropriate Exception level. Attempting to execute an instruction when the value of PSTATE.IL is 1." + }, + { + "ArchStdEvent": "EXC_SVC", + "PublicDescription": "Counts SVC exceptions taken locally." + }, + { + "ArchStdEvent": "EXC_PABORT", + "PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instruction Aborts." + }, + { + "ArchStdEvent": "EXC_DABORT", + "PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SErrors. Conditions that could cause those exceptions are attempting to read or write memory where the MMU generates a fault, attempting to read or write memory with a misaligned address, interrupts from the nSEI inputs and internally generated SErrors." + }, + { + "ArchStdEvent": "EXC_IRQ", + "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are taken locally." + }, + { + "ArchStdEvent": "EXC_FIQ", + "PublicDescription": "Counts FIQ exceptions including the virtual FIQs that are taken locally." + }, + { + "ArchStdEvent": "EXC_SMC", + "PublicDescription": "Counts SMC exceptions take to EL3." + }, + { + "ArchStdEvent": "EXC_HVC", + "PublicDescription": "Counts HVC exceptions taken to EL2." + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC." + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data Aborts or SError interrupts. Conditions that could cause those exceptions are:\n\n1. Attempting to read or write memory where the MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Interrupts from the SEI input.\n4. internally generated SErrors." + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + "PublicDescription": "Counts the number of synchronous trap exceptions which are not taken locally and are not SVC, SMC, HVC, data aborts, Instruction Aborts, or interrupts." + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are not taken locally." + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + "PublicDescription": "Counts FIQs which are not taken locally but taken from EL0, EL1,\n or EL2 to EL3 (which would be the normal behavior for FIQs when not executing\n in EL3)." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/fp_operation.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/fp_operation.json new file mode 100644 index 000000000000..cec3435ac766 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/fp_operation.json @@ -0,0 +1,22 @@ +[ + { + "ArchStdEvent": "FP_HP_SPEC", + "PublicDescription": "Counts speculatively executed half precision floating point operations." + }, + { + "ArchStdEvent": "FP_SP_SPEC", + "PublicDescription": "Counts speculatively executed single precision floating point operations." + }, + { + "ArchStdEvent": "FP_DP_SPEC", + "PublicDescription": "Counts speculatively executed double precision floating point operations." + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC", + "PublicDescription": "Counts speculatively executed scalable single precision floating point operations." + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC", + "PublicDescription": "Counts speculatively executed non-scalable single precision floating point operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/general.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/general.json new file mode 100644 index 000000000000..c5dcdcf43c58 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/general.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES", + "PublicDescription": "Counts CPU clock cycles (not timer cycles). The clock measured by this event is defined as the physical clock driving the CPU logic." + }, + { + "ArchStdEvent": "CNT_CYCLES", + "PublicDescription": "Increments at a constant frequency equal to the rate of increment of the System Counter, CNTPCT_EL0." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1d_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1d_cache.json new file mode 100644 index 000000000000..ee04d9fe1a70 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1d_cache.json @@ -0,0 +1,50 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_REFILL", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE", + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." + }, + { + "ArchStdEvent": "L1D_CACHE_WB", + "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode." + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD", + "PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read operations, that incurred additional latency." + }, + { + "ArchStdEvent": "L1D_CACHE_RD", + "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + "PublicDescription": "Counts level 1 data cache accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by virtual address) instruction. Near atomic operations that resolve in the CPUs caches count as a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + "PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches inside the immediate cluster of the core." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + "PublicDescription": "Counts level 1 data cache refills for which the cache line data came from outside the immediate cluster of the core, like an SLC in the system interconnect or DRAM." + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + "PublicDescription": "Counts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coherency operations from another CPU in the system.\n\nThis event does not count for the following conditions:\n\n1. A cache refill invalidates a cache line.\n2. A CMO which is executed on that CPU and invalidates a cache line specified by set/way.\n\nNote that CMOs that operate by set/way cannot be broadcast from one CPU to another." + }, + { + "ArchStdEvent": "L1D_CACHE_RW", + "PublicDescription": "Counts level 1 data demand cache accesses from any load or store operation. Near atomic operations that resolve in the CPUs caches counts as both a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_HWPRF", + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations generated by the hardware prefetcher." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_HWPRF", + "PublicDescription": "Counts level 1 data cache refills where the cache line is requested by a hardware prefetcher." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1i_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1i_cache.json new file mode 100644 index 000000000000..633f1030359d --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l1i_cache.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL", + "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." + }, + { + "ArchStdEvent": "L1I_CACHE", + "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS", + "PublicDescription": "Counts cache line refills into the level 1 instruction cache, that incurred additional latency." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l2_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l2_cache.json new file mode 100644 index 000000000000..e6cce710c560 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l2_cache.json @@ -0,0 +1,78 @@ +[ + { + "ArchStdEvent": "L2D_CACHE", + "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL", + "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB", + "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line." + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE", + "PublicDescription": "Counts level 2 cache line allocates that do not fetch data from outside the level 2 data or unified cache." + }, + { + "ArchStdEvent": "L2I_CACHE", + "PublicDescription": "Counts accesses to the level 2 cache due to instruction accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level instruction cache." + }, + { + "ArchStdEvent": "L2I_CACHE_REFILL", + "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 instruction cache." + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + "PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + "PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated into the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + "PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n2. Snoop responses or,\n\n3. Direct cache transfers to another CPU due to a forwarding snoop request." + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", + "PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by cache maintenance operations that operate by a virtual address, or by external coherency operations. This event does not count if either:\n\n1. A cache refill invalidates a cache line or,\n2. A Cache Maintenance Operation (CMO), which invalidates a cache line specified by set/way, is executed on that CPU.\n\nCMOs that operate by set/way cannot be broadcast from one CPU to another." + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD", + "PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory read operations that incurred additional latency." + }, + { + "ArchStdEvent": "L2I_CACHE_LMISS", + "PublicDescription": "Counts cache line refills into the level 2 unified cache from any instruction read operations that incurred additional latency." + }, + { + "ArchStdEvent": "L2D_CACHE_RW", + "PublicDescription": "Counts level 2 cache demand accesses from any load/store operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2I_CACHE_RD", + "PublicDescription": "Counts level 2 cache accesses that are due to a demand instruction cache access." + }, + { + "ArchStdEvent": "L2D_CACHE_PRF", + "PublicDescription": "Counts level 2 data cache accesses from software preload or prefetch instructions or hardware prefetcher." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_PRF", + "PublicDescription": "Counts refills due to accesses generated as a result of prefetches." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l3_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l3_cache.json new file mode 100644 index 000000000000..8fe51a628419 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/l3_cache.json @@ -0,0 +1,26 @@ +[ + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE", + "PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores." + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL", + "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." + }, + { + "ArchStdEvent": "L3D_CACHE", + "PublicDescription": "Counts level 3 cache accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L3D_CACHE_RD", + "PublicDescription": "Counts level 3 cache accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD", + "PublicDescription": "Counts any cache line refill into the level 3 cache from memory read operations that incurred additional latency." + }, + { + "ArchStdEvent": "L3D_CACHE_MISS", + "PublicDescription": "Counts level 3 cache accesses that missed in the level 3 cache." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json new file mode 100644 index 000000000000..c9259682d39e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ll_cache.json @@ -0,0 +1,22 @@ +[ + { + "ArchStdEvent": "LL_CACHE", + "PublicDescription": "Counts transactions that were returned from outside the core cluster. This event counts transactions for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts transactions for L3 cache." + }, + { + "ArchStdEvent": "LL_CACHE_MISS", + "PublicDescription": "Counts transactions that were returned from outside the core cluster and missed in the last level cache" + }, + { + "ArchStdEvent": "LL_CACHE_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for the L3 cache. This event counts read transactions returned from outside the core if those transactions are either hit in the system level cache or missed in the SLC and are returned from any other external sources." + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster but missed in the system level cache. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for L3 cache. This event counts read transactions returned from outside the core if those transactions are missed in the System level Cache. The data source of the transaction is indicated by a field in the CHI transaction returning to the CPU. This event does not count reads caused by cache maintenance operations." + }, + { + "ArchStdEvent": "LL_CACHE_REFILL", + "PublicDescription": "Counts last level accesses that receive data from outside the last level cache." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/memory.json new file mode 100644 index 000000000000..f19204a5faae --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/memory.json @@ -0,0 +1,54 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS", + "PublicDescription": "Counts memory accesses issued by the CPU load store unit, where those accesses are issued due to load or store operations. This event counts memory accesses no matter whether the data is received from any level of cache hierarchy or external memory. If memory accesses are broken up into smaller transactions than what were specified in the load or store instructions, then the event counts those smaller memory transactions." + }, + { + "ArchStdEvent": "REMOTE_ACCESS", + "PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mesh in the system. If the CHI bus response back to the core indicates that the data source is from another chip (mesh), then the counter is updated. If no data is returned, even if the system snoops another chip/mesh, then the counter is not updated." + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + "PublicDescription": "Counts memory accesses issued by the CPU due to load operations. The event counts any memory load access, no matter whether the data is received from any level of cache hierarchy or external memory. The event also counts atomic load operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions." + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + "PublicDescription": "Counts memory accesses issued by the CPU due to store operations. The event counts any memory store access, no matter whether the data is located in any level of cache or external memory. The event also counts atomic load and store operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions." + }, + { + "ArchStdEvent": "LDST_ALIGN_LAT", + "PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred additional latency, due to the alignment of the address and the size of data being accessed, which results in store crossing a single cache line." + }, + { + "ArchStdEvent": "LD_ALIGN_LAT", + "PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed, which results in load crossing a single cache line." + }, + { + "ArchStdEvent": "ST_ALIGN_LAT", + "PublicDescription": "Counts the number of memory write access in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed incurred additional latency." + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED", + "PublicDescription": "Counts the number of memory read and write accesses counted by MEM_ACCESS that are tag checked by the Memory Tagging Extension (MTE). This event is implemented as the sum of MEM_ACCESS_CHECKED_RD and MEM_ACCESS_CHECKED_WR" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_RD", + "PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by the Memory Tagging Extension (MTE)." + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_WR", + "PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by the Memory Tagging Extension (MTE)." + }, + { + "ArchStdEvent": "INST_FETCH_PERCYC", + "PublicDescription": "Counts number of instruction fetches outstanding per cycle, which will provide an average latency of instruction fetch." + }, + { + "ArchStdEvent": "MEM_ACCESS_RD_PERCYC", + "PublicDescription": "Counts the number of outstanding loads or memory read accesses per cycle." + }, + { + "ArchStdEvent": "INST_FETCH", + "PublicDescription": "Counts Instruction memory accesses that the PE makes." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json new file mode 100644 index 000000000000..eb3a35f244e7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/metrics.json @@ -0,0 +1,457 @@ +[ + { + "ArchStdEvent": "backend_bound" + }, + { + "MetricName": "backend_busy_bound", + "MetricExpr": "STALL_BACKEND_BUSY / STALL_BACKEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to issue queues being full to accept operations for execution.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_cache_l1d_bound", + "MetricExpr": "STALL_BACKEND_L1D / (STALL_BACKEND_L1D + STALL_BACKEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by level 1 data cache misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_cache_l2d_bound", + "MetricExpr": "STALL_BACKEND_MEM / (STALL_BACKEND_L1D + STALL_BACKEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by level 2 data cache misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_core_bound", + "MetricExpr": "STALL_BACKEND_CPUBOUND / STALL_BACKEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend core resource constraints not related to instruction fetch latency issues caused by memory access components.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_core_rename_bound", + "MetricExpr": "STALL_BACKEND_RENAME / STALL_BACKEND_CPUBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend as the rename unit registers are unavailable.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_bound", + "MetricExpr": "STALL_BACKEND_MEMBOUND / STALL_BACKEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend core resource constraints related to memory access latency issues caused by memory access components.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_cache_bound", + "MetricExpr": "(STALL_BACKEND_L1D + STALL_BACKEND_MEM) / STALL_BACKEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory latency issues caused by data cache misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_store_bound", + "MetricExpr": "STALL_BACKEND_ST / STALL_BACKEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory write pending caused by stores stalled in the pre-commit stage.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_tlb_bound", + "MetricExpr": "STALL_BACKEND_TLB / STALL_BACKEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by data TLB misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_stalled_cycles", + "MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "ArchStdEvent": "bad_speculation", + "MetricExpr": "(1 - STALL_SLOT / (5 * CPU_CYCLES)) * (1 - OP_RETIRED / OP_SPEC) * 100 + STALL_FRONTEND_FLUSH / CPU_CYCLES * 100" + }, + { + "MetricName": "barrier_percentage", + "MetricExpr": "(ISB_SPEC + DSB_SPEC + DMB_SPEC) / INST_SPEC * 100", + "BriefDescription": "This metric measures instruction and data barrier operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "branch_direct_ratio", + "MetricExpr": "BR_IMMED_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of direct branches retired to the total number of branches architecturally executed.", + "MetricGroup": "Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "branch_indirect_ratio", + "MetricExpr": "BR_IND_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of indirect branches retired, including function returns, to the total number of branches architecturally executed.", + "MetricGroup": "Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "branch_misprediction_ratio", + "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.", + "MetricGroup": "Miss_Ratio;Branch_Effectiveness", + "ScaleUnit": "100percent of branches" + }, + { + "MetricName": "branch_mpki", + "MetricExpr": "BR_MIS_PRED_RETIRED / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.", + "MetricGroup": "MPKI;Branch_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "branch_percentage", + "MetricExpr": "PC_WRITE_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures branch operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "branch_return_ratio", + "MetricExpr": "BR_RETURN_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of branches retired that are function returns to the total number of branches architecturally executed.", + "MetricGroup": "Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "crypto_percentage", + "MetricExpr": "CRYPTO_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "dtlb_mpki", + "MetricExpr": "DTLB_WALK / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "dtlb_walk_ratio", + "MetricExpr": "DTLB_WALK / L1D_TLB", + "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "fp16_percentage", + "MetricExpr": "FP_HP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures half-precision floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "FP_Precision_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "fp32_percentage", + "MetricExpr": "FP_SP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures single-precision floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "FP_Precision_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "fp64_percentage", + "MetricExpr": "FP_DP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures double-precision floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "FP_Precision_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "fp_ops_per_cycle", + "MetricExpr": "(FP_SCALE_OPS_SPEC + FP_FIXED_OPS_SPEC) / CPU_CYCLES", + "BriefDescription": "This metric measures floating point operations per cycle in any precision performed by any instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.", + "MetricGroup": "FP_Arithmetic_Intensity", + "ScaleUnit": "1operations per cycle" + }, + { + "ArchStdEvent": "frontend_bound", + "MetricExpr": "(STALL_SLOT_FRONTEND / (5 * CPU_CYCLES) - STALL_FRONTEND_FLUSH / CPU_CYCLES) * 100" + }, + { + "MetricName": "frontend_cache_l1i_bound", + "MetricExpr": "STALL_FRONTEND_L1I / (STALL_FRONTEND_L1I + STALL_FRONTEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory access latency issues caused by level 1 instruction cache misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_cache_l2i_bound", + "MetricExpr": "STALL_FRONTEND_MEM / (STALL_FRONTEND_L1I + STALL_FRONTEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory access latency issues caused by level 2 instruction cache misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_core_bound", + "MetricExpr": "STALL_FRONTEND_CPUBOUND / STALL_FRONTEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to frontend core resource constraints not related to instruction fetch latency issues caused by memory access components.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_core_flow_bound", + "MetricExpr": "STALL_FRONTEND_FLOW / STALL_FRONTEND_CPUBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend as the decode unit is awaiting input from the branch prediction unit.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_core_flush_bound", + "MetricExpr": "STALL_FRONTEND_FLUSH / STALL_FRONTEND_CPUBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend as the processor is recovering from a pipeline flush caused by bad speculation or other machine resteers.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_mem_bound", + "MetricExpr": "STALL_FRONTEND_MEMBOUND / STALL_FRONTEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to frontend core resource constraints related to the instruction fetch latency issues caused by memory access components.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_mem_cache_bound", + "MetricExpr": "(STALL_FRONTEND_L1I + STALL_FRONTEND_MEM) / STALL_FRONTEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to instruction fetch latency issues caused by instruction cache misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_mem_tlb_bound", + "MetricExpr": "STALL_FRONTEND_TLB / STALL_FRONTEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to instruction fetch latency issues caused by instruction TLB misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_stalled_cycles", + "MetricExpr": "STALL_FRONTEND / CPU_CYCLES * 100", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "integer_dp_percentage", + "MetricExpr": "(DP_SPEC - DSB_SPEC) / INST_SPEC * 100", + "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "ipc", + "MetricExpr": "INST_RETIRED / CPU_CYCLES", + "BriefDescription": "This metric measures the number of instructions retired per cycle.", + "MetricGroup": "General", + "ScaleUnit": "1per cycle" + }, + { + "MetricName": "itlb_mpki", + "MetricExpr": "ITLB_WALK / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "itlb_walk_ratio", + "MetricExpr": "ITLB_WALK / L1I_TLB", + "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1d_cache_miss_ratio", + "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", + "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", + "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l1d_cache_mpki", + "MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1D_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1d_tlb_miss_ratio", + "MetricExpr": "L1D_TLB_REFILL / L1D_TLB", + "BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1d_tlb_mpki", + "MetricExpr": "L1D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_cache_miss_ratio", + "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", + "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", + "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l1i_cache_mpki", + "MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1I_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_tlb_miss_ratio", + "MetricExpr": "L1I_TLB_REFILL / L1I_TLB", + "BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1i_tlb_mpki", + "MetricExpr": "L1I_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_cache_miss_ratio", + "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", + "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l2_cache_mpki", + "MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "MPKI;L2_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_tlb_miss_ratio", + "MetricExpr": "L2D_TLB_REFILL / L2D_TLB", + "BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l2_tlb_mpki", + "MetricExpr": "L2D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "ll_cache_read_hit_ratio", + "MetricExpr": "(LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD", + "BriefDescription": "This metric measures the ratio of last level cache read accesses hit in the cache to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", + "MetricGroup": "LL_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "ll_cache_read_miss_ratio", + "MetricExpr": "LL_CACHE_MISS_RD / LL_CACHE_RD", + "BriefDescription": "This metric measures the ratio of last level cache read accesses missed to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", + "MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "ll_cache_read_mpki", + "MetricExpr": "LL_CACHE_MISS_RD / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of last level cache read accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;LL_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "load_percentage", + "MetricExpr": "LD_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "nonsve_fp_ops_per_cycle", + "MetricExpr": "FP_FIXED_OPS_SPEC / CPU_CYCLES", + "BriefDescription": "This metric measures floating point operations per cycle in any precision performed by an instruction that is not an SVE instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.", + "MetricGroup": "FP_Arithmetic_Intensity", + "ScaleUnit": "1operations per cycle" + }, + { + "ArchStdEvent": "retiring" + }, + { + "MetricName": "scalar_fp_percentage", + "MetricExpr": "VFP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "simd_percentage", + "MetricExpr": "ASE_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "store_percentage", + "MetricExpr": "ST_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_all_percentage", + "MetricExpr": "SVE_INST_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations, including loads and stores, as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_fp_ops_per_cycle", + "MetricExpr": "FP_SCALE_OPS_SPEC / CPU_CYCLES", + "BriefDescription": "This metric measures floating point operations per cycle in any precision performed by SVE instructions. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.", + "MetricGroup": "FP_Arithmetic_Intensity", + "ScaleUnit": "1operations per cycle" + }, + { + "MetricName": "sve_predicate_empty_percentage", + "MetricExpr": "SVE_PRED_EMPTY_SPEC / SVE_PRED_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with no active predicates as a percentage of sve predicated operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_predicate_full_percentage", + "MetricExpr": "SVE_PRED_FULL_SPEC / SVE_PRED_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with all active predicates as a percentage of sve predicated operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_predicate_partial_percentage", + "MetricExpr": "SVE_PRED_PARTIAL_SPEC / SVE_PRED_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with at least one active predicates as a percentage of sve predicated operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_predicate_percentage", + "MetricExpr": "SVE_PRED_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with predicates as a percentage of operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/retired.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/retired.json new file mode 100644 index 000000000000..135e5dbd8c78 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/retired.json @@ -0,0 +1,90 @@ +[ + { + "ArchStdEvent": "SW_INCR", + "PublicDescription": "Counts software writes to the PMSWINC_EL0 (software PMU increment) register. The PMSWINC_EL0 register is a manually updated counter for use by application software.\n\nThis event could be used to measure any user program event, such as accesses to a particular data structure (by writing to the PMSWINC_EL0 register each time the data structure is accessed).\n\nTo use the PMSWINC_EL0 register and event, developers must insert instructions that write to the PMSWINC_EL0 register into the source code.\n\nSince the SW_INCR event records writes to the PMSWINC_EL0 register, there is no need to do a read/increment/write sequence to the PMSWINC_EL0 register." + }, + { + "ArchStdEvent": "INST_RETIRED", + "PublicDescription": "Counts instructions that have been architecturally executed." + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED", + "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR_EL1 register, which usually contain the kernel PID and can be output with hardware trace." + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED", + "PublicDescription": "Counts branch instructions that caused a change of Program Counter, which effectively causes a change in the control flow of the program." + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches." + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED", + "PublicDescription": "Counts architecturally executed procedure returns." + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED", + "PublicDescription": "Counts architectural writes to TTBR0/1_EL1. If virtualization host extensions are enabled (by setting the HCR_EL2.E2H bit to 1), then accesses to TTBR0/1_EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers are typically updated when the kernel is swapping user-space threads or applications." + }, + { + "ArchStdEvent": "BR_RETIRED", + "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted. Note that exception generating instructions, exception return instructions and context synchronization instructions are not counted." + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED", + "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "OP_RETIRED", + "PublicDescription": "Counts micro-operations that are architecturally executed. This is a count of number of micro-operations retired from the commit queue in a single cycle." + }, + { + "ArchStdEvent": "BR_IMMED_TAKEN_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches that were taken." + }, + { + "ArchStdEvent": "BR_INDNR_TAKEN_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were taken." + }, + { + "ArchStdEvent": "BR_IMMED_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches that were correctly predicted." + }, + { + "ArchStdEvent": "BR_IMMED_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_IND_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were correctly predicted." + }, + { + "ArchStdEvent": "BR_IND_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_RETURN_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed procedure returns that were correctly predicted." + }, + { + "ArchStdEvent": "BR_RETURN_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed procedure returns that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_INDNR_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were correctly predicted." + }, + { + "ArchStdEvent": "BR_INDNR_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_PRED_RETIRED", + "PublicDescription": "Counts branch instructions counted by BR_RETIRED which were correctly predicted." + }, + { + "ArchStdEvent": "BR_IND_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches including procedure returns." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/spe.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/spe.json new file mode 100644 index 000000000000..ca0217fa4681 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/spe.json @@ -0,0 +1,42 @@ +[ + { + "ArchStdEvent": "SAMPLE_POP", + "PublicDescription": "Counts statistical profiling sample population, the count of all operations that could be sampled but may or may not be chosen for sampling." + }, + { + "ArchStdEvent": "SAMPLE_FEED", + "PublicDescription": "Counts statistical profiling samples taken for sampling." + }, + { + "ArchStdEvent": "SAMPLE_FILTRATE", + "PublicDescription": "Counts statistical profiling samples taken which are not removed by filtering." + }, + { + "ArchStdEvent": "SAMPLE_COLLISION", + "PublicDescription": "Counts statistical profiling samples that have collided with a previous sample and so therefore not taken." + }, + { + "ArchStdEvent": "SAMPLE_FEED_BR", + "PublicDescription": "Counts statistical profiling samples taken which are branches." + }, + { + "ArchStdEvent": "SAMPLE_FEED_LD", + "PublicDescription": "Counts statistical profiling samples taken which are loads or load atomic operations." + }, + { + "ArchStdEvent": "SAMPLE_FEED_ST", + "PublicDescription": "Counts statistical profiling samples taken which are stores or store atomic operations." + }, + { + "ArchStdEvent": "SAMPLE_FEED_OP", + "PublicDescription": "Counts statistical profiling samples taken which are matching any operation type filters supported." + }, + { + "ArchStdEvent": "SAMPLE_FEED_EVENT", + "PublicDescription": "Counts statistical profiling samples taken which are matching event packet filter constraints." + }, + { + "ArchStdEvent": "SAMPLE_FEED_LAT", + "PublicDescription": "Counts statistical profiling samples taken which are exceeding minimum latency set by operation latency filter constraints." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/spec_operation.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/spec_operation.json new file mode 100644 index 000000000000..f91eb18d683c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/spec_operation.json @@ -0,0 +1,90 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED", + "PublicDescription": "Counts branches which are speculatively executed and mispredicted." + }, + { + "ArchStdEvent": "BR_PRED", + "PublicDescription": "Counts all speculatively executed branches." + }, + { + "ArchStdEvent": "INST_SPEC", + "PublicDescription": "Counts operations that have been speculatively executed." + }, + { + "ArchStdEvent": "OP_SPEC", + "PublicDescription": "Counts micro-operations speculatively executed. This is the count of the number of micro-operations dispatched in a cycle." + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed and have not successfully completed the store operation." + }, + { + "ArchStdEvent": "STREX_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed." + }, + { + "ArchStdEvent": "LD_SPEC", + "PublicDescription": "Counts speculatively executed load operations including Single Instruction Multiple Data (SIMD) load operations." + }, + { + "ArchStdEvent": "ST_SPEC", + "PublicDescription": "Counts speculatively executed store operations including Single Instruction Multiple Data (SIMD) store operations." + }, + { + "ArchStdEvent": "DP_SPEC", + "PublicDescription": "Counts speculatively executed logical or arithmetic instructions such as MOV/MVN operations." + }, + { + "ArchStdEvent": "ASE_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD operations excluding load, store and move micro-operations that move data to or from SIMD (vector) registers." + }, + { + "ArchStdEvent": "VFP_SPEC", + "PublicDescription": "Counts speculatively executed floating point operations. This event does not count operations that move data to or from floating point (vector) registers." + }, + { + "ArchStdEvent": "PC_WRITE_SPEC", + "PublicDescription": "Counts speculatively executed operations which cause software changes of the PC. Those operations include all taken branch operations." + }, + { + "ArchStdEvent": "CRYPTO_SPEC", + "PublicDescription": "Counts speculatively executed cryptographic operations except for PMULL and VMULL operations." + }, + { + "ArchStdEvent": "ISB_SPEC", + "PublicDescription": "Counts ISB operations that are executed." + }, + { + "ArchStdEvent": "DSB_SPEC", + "PublicDescription": "Counts DSB operations that are speculatively issued to Load/Store unit in the CPU." + }, + { + "ArchStdEvent": "DMB_SPEC", + "PublicDescription": "Counts DMB operations that are speculatively issued to the Load/Store unit in the CPU. This event does not count implied barriers from load acquire/store release operations." + }, + { + "ArchStdEvent": "RC_LD_SPEC", + "PublicDescription": "Counts any load acquire operations that are speculatively executed. For example: LDAR, LDARH, LDARB" + }, + { + "ArchStdEvent": "RC_ST_SPEC", + "PublicDescription": "Counts any store release operations that are speculatively executed. For example: STLR, STLRH, STLRB" + }, + { + "ArchStdEvent": "ASE_INST_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD operations." + }, + { + "ArchStdEvent": "CAS_NEAR_PASS", + "PublicDescription": "Counts compare and swap instructions that executed locally to the PE and updated the location accessed." + }, + { + "ArchStdEvent": "CAS_NEAR_SPEC", + "PublicDescription": "Counts compare and swap instructions that executed locally to the PE." + }, + { + "ArchStdEvent": "CAS_FAR_SPEC", + "PublicDescription": "Counts compare and swap instructions that did not execute locally to the PE." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/stall.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/stall.json new file mode 100644 index 000000000000..51cda27880b9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/stall.json @@ -0,0 +1,86 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND", + "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. STALL_FRONTEND_SLOTS counts SLOTS during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL_BACKEND", + "PublicDescription": "Counts cycles whenever the rename unit is unable to send any micro-operations to the backend of the pipeline because of backend resource constraints. Backend resource constraints can include issue stage fullness, execution stage fullness, or other internal pipeline resource fullness. All the backend slots were empty during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL", + "PublicDescription": "Counts cycles when no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). This event is the sum of STALL_FRONTEND and STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND", + "PublicDescription": "Counts slots per cycle in which no operations are sent from the rename unit to the backend due to backend resource constraints. STALL_BACKEND counts during the cycle when STALL_SLOT_BACKEND counts at least 1." + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND", + "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend due to frontend resource constraints." + }, + { + "ArchStdEvent": "STALL_SLOT", + "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). STALL_SLOT is the sum of STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND." + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM", + "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the last level core cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_MEMBOUND", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the memory resources." + }, + { + "ArchStdEvent": "STALL_FRONTEND_L1I", + "PublicDescription": "Counts cycles when the frontend is stalled because there is an instruction fetch request pending in the level 1 instruction cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_MEM", + "PublicDescription": "Counts cycles when the frontend is stalled because there is an instruction fetch request pending in the last level core cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_TLB", + "PublicDescription": "Counts when the frontend is stalled on any TLB misses being handled. This event also counts the TLB accesses made by hardware prefetches." + }, + { + "ArchStdEvent": "STALL_FRONTEND_CPUBOUND", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the CPU resources excluding memory resources." + }, + { + "ArchStdEvent": "STALL_FRONTEND_FLOW", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the branch prediction unit." + }, + { + "ArchStdEvent": "STALL_FRONTEND_FLUSH", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage as the frontend is recovering from a machine flush or resteer. Example scenarios that cause a flush include branch mispredictions, taken exceptions, micro-architectural flush etc." + }, + { + "ArchStdEvent": "STALL_BACKEND_MEMBOUND", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to resource constraints in the memory resources." + }, + { + "ArchStdEvent": "STALL_BACKEND_L1D", + "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the level 1 data cache." + }, + { + "ArchStdEvent": "STALL_BACKEND_TLB", + "PublicDescription": "Counts cycles when the backend is stalled on any demand TLB misses being handled." + }, + { + "ArchStdEvent": "STALL_BACKEND_ST", + "PublicDescription": "Counts cycles when the backend is stalled and there is a store that has not reached the pre-commit stage." + }, + { + "ArchStdEvent": "STALL_BACKEND_CPUBOUND", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to any resource constraints in the CPU excluding memory resources." + }, + { + "ArchStdEvent": "STALL_BACKEND_BUSY", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations because the issue queues are full to take any operations for execution." + }, + { + "ArchStdEvent": "STALL_BACKEND_RENAME", + "PublicDescription": "Counts cycles when backend is stalled even when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/sve.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/sve.json new file mode 100644 index 000000000000..51dab48cb2ba --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/sve.json @@ -0,0 +1,50 @@ +[ + { + "ArchStdEvent": "SVE_INST_SPEC", + "PublicDescription": "Counts speculatively executed operations that are SVE operations." + }, + { + "ArchStdEvent": "SVE_PRED_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations." + }, + { + "ArchStdEvent": "SVE_PRED_EMPTY_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with no active predicate elements." + }, + { + "ArchStdEvent": "SVE_PRED_FULL_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with all predicate elements active." + }, + { + "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with at least one but not all active predicate elements." + }, + { + "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with at least one non active predicate elements." + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC", + "PublicDescription": "Counts speculatively executed SVE first fault or non-fault load operations." + }, + { + "ArchStdEvent": "SVE_LDFF_FAULT_SPEC", + "PublicDescription": "Counts speculatively executed SVE first fault or non-fault load operations that clear at least one bit in the FFR." + }, + { + "ArchStdEvent": "ASE_SVE_INT8_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type an 8-bit integer." + }, + { + "ArchStdEvent": "ASE_SVE_INT16_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type a 16-bit integer." + }, + { + "ArchStdEvent": "ASE_SVE_INT32_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type a 32-bit integer." + }, + { + "ArchStdEvent": "ASE_SVE_INT64_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type a 64-bit integer." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/tlb.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/tlb.json new file mode 100644 index 000000000000..c7aa89c2f19f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/tlb.json @@ -0,0 +1,74 @@ +[ + { + "ArchStdEvent": "L1I_TLB_REFILL", + "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL", + "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction." + }, + { + "ArchStdEvent": "L1D_TLB", + "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1I_TLB", + "PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This event counts both demand accesses and prefetch or preload generated accesses." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL", + "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches." + }, + { + "ArchStdEvent": "L2D_TLB", + "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK", + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK_PERCYC", + "PublicDescription": "Counts the number of data translation table walks in progress per cycle." + }, + { + "ArchStdEvent": "ITLB_WALK_PERCYC", + "PublicDescription": "Counts the number of instruction translation table walks in progress per cycle." + }, + { + "ArchStdEvent": "DTLB_HWUPD", + "PublicDescription": "Counts number of memory accesses triggered by a data translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers." + }, + { + "ArchStdEvent": "ITLB_HWUPD", + "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD." + }, + { + "ArchStdEvent": "DTLB_STEP", + "PublicDescription": "Counts number of memory accesses triggered by a demand data translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers." + }, + { + "ArchStdEvent": "ITLB_STEP", + "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD." + }, + { + "ArchStdEvent": "DTLB_WALK_LARGE", + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_BLOCK is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK_LARGE", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. In this family, this is equal to ITLB_WALK_BLOCK event. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK_SMALL", + "PublicDescription": "Counts number of data translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_PAGE event is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK_SMALL", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. In this family, this is equal to ITLB_WALK_PAGE event. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/trace.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/trace.json new file mode 100644 index 000000000000..a09043486cd9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/trace.json @@ -0,0 +1,42 @@ +[ + { + "ArchStdEvent": "TRB_WRAP", + "PublicDescription": "This event is generated each time the current write pointer is wrapped to the base pointer." + }, + { + "ArchStdEvent": "TRB_TRIG", + "PublicDescription": "This event is generated when a Trace Buffer Extension Trigger Event occurs." + }, + { + "ArchStdEvent": "TRCEXTOUT0", + "PublicDescription": "This event is generated each time an event is signaled by ETE external event 0." + }, + { + "ArchStdEvent": "TRCEXTOUT1", + "PublicDescription": "This event is generated each time an event is signaled by ETE external event 1." + }, + { + "ArchStdEvent": "TRCEXTOUT2", + "PublicDescription": "This event is generated each time an event is signaled by ETE external event 2." + }, + { + "ArchStdEvent": "TRCEXTOUT3", + "PublicDescription": "This event is generated each time an event is signaled by ETE external event 3." + }, + { + "ArchStdEvent": "CTI_TRIGOUT4", + "PublicDescription": "This event is generated each time an event is signaled on CTI output trigger 4." + }, + { + "ArchStdEvent": "CTI_TRIGOUT5", + "PublicDescription": "This event is generated each time an event is signaled on CTI output trigger 5." + }, + { + "ArchStdEvent": "CTI_TRIGOUT6", + "PublicDescription": "This event is generated each time an event is signaled on CTI output trigger 6." + }, + { + "ArchStdEvent": "CTI_TRIGOUT7", + "PublicDescription": "This event is generated each time an event is signaled on CTI output trigger 7." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/brbe.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/brbe.json new file mode 100644 index 000000000000..9fdf5b0453a0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/brbe.json @@ -0,0 +1,6 @@ +[ + { + "ArchStdEvent": "BRB_FILTRATE", + "PublicDescription": "Counts branch records captured which are not removed by filtering." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/bus.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/bus.json new file mode 100644 index 000000000000..2e11a8c4a484 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/bus.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "BUS_ACCESS", + "PublicDescription": "Counts memory transactions issued by the CPU to the external bus, including snoop requests and snoop responses. Each beat of data is counted individually." + }, + { + "ArchStdEvent": "BUS_CYCLES", + "PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES." + }, + { + "ArchStdEvent": "BUS_ACCESS_RD", + "PublicDescription": "Counts memory read transactions seen on the external bus. Each beat of data is counted individually." + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + "PublicDescription": "Counts memory write transactions seen on the external bus. Each beat of data is counted individually." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/exception.json new file mode 100644 index 000000000000..7126fbf292e0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/exception.json @@ -0,0 +1,62 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN", + "PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally." + }, + { + "ArchStdEvent": "EXC_RETURN", + "PublicDescription": "Counts any architecturally executed exception return instructions. For example: AArch64: ERET" + }, + { + "ArchStdEvent": "EXC_UNDEF", + "PublicDescription": "Counts the number of synchronous exceptions which are taken locally that are due to attempting to execute an instruction that is UNDEFINED. Attempting to execute instruction bit patterns that have not been allocated. Attempting to execute instructions when they are disabled. Attempting to execute instructions at an inappropriate Exception level. Attempting to execute an instruction when the value of PSTATE.IL is 1." + }, + { + "ArchStdEvent": "EXC_SVC", + "PublicDescription": "Counts SVC exceptions taken locally." + }, + { + "ArchStdEvent": "EXC_PABORT", + "PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instruction Aborts." + }, + { + "ArchStdEvent": "EXC_DABORT", + "PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SErrors. Conditions that could cause those exceptions are attempting to read or write memory where the MMU generates a fault, attempting to read or write memory with a misaligned address, interrupts from the nSEI inputs and internally generated SErrors." + }, + { + "ArchStdEvent": "EXC_IRQ", + "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are taken locally." + }, + { + "ArchStdEvent": "EXC_FIQ", + "PublicDescription": "Counts FIQ exceptions including the virtual FIQs that are taken locally." + }, + { + "ArchStdEvent": "EXC_SMC", + "PublicDescription": "Counts SMC exceptions take to EL3." + }, + { + "ArchStdEvent": "EXC_HVC", + "PublicDescription": "Counts HVC exceptions taken to EL2." + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC." + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data Aborts or SError interrupts. Conditions that could cause those exceptions are:\n\n1. Attempting to read or write memory where the MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Interrupts from the SEI input.\n4. internally generated SErrors." + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + "PublicDescription": "Counts the number of synchronous trap exceptions which are not taken locally and are not SVC, SMC, HVC, data aborts, Instruction Aborts, or interrupts." + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are not taken locally." + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + "PublicDescription": "Counts FIQs which are not taken locally but taken from EL0, EL1,\n or EL2 to EL3 (which would be the normal behavior for FIQs when not executing\n in EL3)." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/fp_operation.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/fp_operation.json new file mode 100644 index 000000000000..cec3435ac766 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/fp_operation.json @@ -0,0 +1,22 @@ +[ + { + "ArchStdEvent": "FP_HP_SPEC", + "PublicDescription": "Counts speculatively executed half precision floating point operations." + }, + { + "ArchStdEvent": "FP_SP_SPEC", + "PublicDescription": "Counts speculatively executed single precision floating point operations." + }, + { + "ArchStdEvent": "FP_DP_SPEC", + "PublicDescription": "Counts speculatively executed double precision floating point operations." + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC", + "PublicDescription": "Counts speculatively executed scalable single precision floating point operations." + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC", + "PublicDescription": "Counts speculatively executed non-scalable single precision floating point operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/general.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/general.json new file mode 100644 index 000000000000..4d816015b8c2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/general.json @@ -0,0 +1,40 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES", + "PublicDescription": "Counts CPU clock cycles (not timer cycles). The clock measured by this event is defined as the physical clock driving the CPU logic." + }, + { + "PublicDescription": "Count of RXDAT or RXRSP responses received with indication completer fullness indicator set to 0", + "EventCode": "0x198", + "EventName": "L2_CHI_CBUSY0", + "BriefDescription": "Number of RXDAT or RXRSP response received with CBusy of 0" + }, + { + "PublicDescription": "Count of RXDAT or RXRSP responses received with indication completer fullness indicator set to 1", + "EventCode": "0x199", + "EventName": "L2_CHI_CBUSY1", + "BriefDescription": "Number of RXDAT or RXRSP response received with CBusy of 1" + }, + { + "PublicDescription": "Count of RXDAT or RXRSP responses received with indication completer fullness indicator set to 2", + "EventCode": "0x19A", + "EventName": "L2_CHI_CBUSY2", + "BriefDescription": "Number of RXDAT or RXRSP response received with CBusy of 2" + }, + { + "PublicDescription": "Count of RXDAT or RXRSP responses received with indication completer fullness indicator set to 3", + "EventCode": "0x19B", + "EventName": "L2_CHI_CBUSY3", + "BriefDescription": "Number of RXDAT or RXRSP response received with CBusy of 3" + }, + { + "PublicDescription": "Count of RXDAT or RXRSP responses received with indication completer indicating multiple cores actively making requests", + "EventCode": "0x19C", + "EventName": "L2_CHI_CBUSY_MT", + "BriefDescription": "Number of RXDAT or RXRSP response received with CBusy Multi-threaded set" + }, + { + "ArchStdEvent": "CNT_CYCLES", + "PublicDescription": "Increments at a constant frequency equal to the rate of increment of the System Counter, CNTPCT_EL0." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l1d_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l1d_cache.json new file mode 100644 index 000000000000..891e07631c6e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l1d_cache.json @@ -0,0 +1,74 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_REFILL", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE", + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." + }, + { + "ArchStdEvent": "L1D_CACHE_WB", + "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode." + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD", + "PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read operations, that incurred additional latency." + }, + { + "ArchStdEvent": "L1D_CACHE_RD", + "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + "PublicDescription": "Counts level 1 data cache accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by virtual address) instruction. Near atomic operations that resolve in the CPUs caches count as a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load instructions where the memory read operation misses in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed store instructions where the memory write operation misses in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + "PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches inside the immediate cluster of the core." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + "PublicDescription": "Counts level 1 data cache refills for which the cache line data came from outside the immediate cluster of the core, like an SLC in the system interconnect or DRAM." + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + "PublicDescription": "Counts dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. This event does not count evictions caused by cache maintenance operations." + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + "PublicDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency operation made by another CPU. Event count includes cache maintenance operations." + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + "PublicDescription": "Counts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coherency operations from another CPU in the system.\n\nThis event does not count for the following conditions:\n\n1. A cache refill invalidates a cache line.\n2. A CMO which is executed on that CPU and invalidates a cache line specified by set/way.\n\nNote that CMOs that operate by set/way cannot be broadcast from one CPU to another." + }, + { + "ArchStdEvent": "L1D_CACHE_RW", + "PublicDescription": "Counts level 1 data demand cache accesses from any load or store operation. Near atomic operations that resolve in the CPUs caches counts as both a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_PRFM", + "PublicDescription": "Counts level 1 data cache accesses from software preload or prefetch instructions." + }, + { + "ArchStdEvent": "L1D_CACHE_MISS", + "PublicDescription": "Counts cache line misses in the level 1 data cache." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_PRFM", + "PublicDescription": "Counts level 1 data cache refills where the cache line access was generated by software preload or prefetch instructions." + }, + { + "ArchStdEvent": "L1D_CACHE_HWPRF", + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations generated by the hardware prefetcher." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l1i_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l1i_cache.json new file mode 100644 index 000000000000..fc511c5d2021 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l1i_cache.json @@ -0,0 +1,62 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL", + "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." + }, + { + "ArchStdEvent": "L1I_CACHE", + "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS", + "PublicDescription": "Counts cache line refills into the level 1 instruction cache, that incurred additional latency." + }, + { + "ArchStdEvent": "L1I_CACHE_RD", + "PublicDescription": "Counts demand instruction fetches which access the level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_PRFM", + "PublicDescription": "Counts instruction fetches generated by software preload or prefetch instructions which access the level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_HWPRF", + "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache generated by the hardware prefetcher." + }, + { + "ArchStdEvent": "L1I_CACHE_REFILL_PRFM", + "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch generated by software preload or prefetch instructions. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT_RD", + "PublicDescription": "Counts demand instruction fetches that access the level 1 instruction cache and hit in the L1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT_RD_FPRFM", + "PublicDescription": "Counts demand instruction fetches that access the level 1 instruction cache that hit in the L1 instruction cache and the line was requested by a software prefetch." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT_RD_FHWPRF", + "PublicDescription": "Counts demand instruction fetches generated by hardware prefetch that access the level 1 instruction cache and hit in the L1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT", + "PublicDescription": "Counts instruction fetches that access the level 1 instruction cache and hit in the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT_PRFM", + "PublicDescription": "Counts instruction fetches generated by software preload or prefetch instructions that access the level 1 instruction cache and hit in the level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_LFB_HIT_RD", + "PublicDescription": "Counts demand instruction fetches that access the level 1 instruction cache and hit in a line that is in the process of being loaded into the level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_LFB_HIT_RD_FPRFM", + "PublicDescription": "Counts demand instruction fetches generated by software prefetch instructions that access the level 1 instruction cache and hit in a line that is in the process of being loaded into the level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_LFB_HIT_RD_FHWPRF", + "PublicDescription": "Counts demand instruction fetches generated by hardware prefetch that access the level 1 instruction cache and hit in a line that is in the process of being loaded into the level 1 instruction cache." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l2_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l2_cache.json new file mode 100644 index 000000000000..b38d71fd1136 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/l2_cache.json @@ -0,0 +1,78 @@ +[ + { + "ArchStdEvent": "L2D_CACHE", + "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL", + "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB", + "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line." + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + "PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + "PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated into the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + "PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n2. Snoop responses or,\n\n3. Direct cache transfers to another CPU due to a forwarding snoop request." + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", + "PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by cache maintenance operations that operate by a virtual address, or by external coherency operations. This event does not count if either:\n\n1. A cache refill invalidates a cache line or,\n2. A Cache Maintenance Operation (CMO), which invalidates a cache line specified by set/way, is executed on that CPU.\n\nCMOs that operate by set/way cannot be broadcast from one CPU to another." + }, + { + "PublicDescription": "Counts level 2 cache accesses due to level 1 data cache hardware prefetcher.", + "EventCode": "0x1B8", + "EventName": "L2D_CACHE_L1HWPRF", + "BriefDescription": "L2D cache access due to L1 hardware prefetch" + }, + { + "PublicDescription": "Counts level 2 cache refills where the cache line is requested by a level 1 data cache hardware prefetcher.", + "EventCode": "0x1B9", + "EventName": "L2D_CACHE_REFILL_L1HWPRF", + "BriefDescription": "L2D cache refill due to L1 hardware prefetch" + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD", + "PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory read operations that incurred additional latency." + }, + { + "ArchStdEvent": "L2D_CACHE_RW", + "PublicDescription": "Counts level 2 cache demand accesses from any load/store operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_PRFM", + "PublicDescription": "Counts level 2 data cache accesses generated by software preload or prefetch instructions." + }, + { + "ArchStdEvent": "L2D_CACHE_MISS", + "PublicDescription": "Counts cache line misses in the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_PRFM", + "PublicDescription": "Counts refills due to accesses generated as a result of software preload or prefetch instructions as counted by L2D_CACHE_PRFM." + }, + { + "ArchStdEvent": "L2D_CACHE_HWPRF", + "PublicDescription": "Counts level 2 data cache accesses generated by L2D hardware prefetchers." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ll_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ll_cache.json new file mode 100644 index 000000000000..fd5a2e0099b8 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ll_cache.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "LL_CACHE_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for the L3 cache. This event counts read transactions returned from outside the core if those transactions are either hit in the system level cache or missed in the SLC and are returned from any other external sources." + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster but missed in the system level cache. This event counts for external last level cache when the system register CPUECTLR.EXTLLC bit is set, otherwise it counts for L3 cache. This event counts read transactions returned from outside the core if those transactions are missed in the System level Cache. The data source of the transaction is indicated by a field in the CHI transaction returning to the CPU. This event does not count reads caused by cache maintenance operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/memory.json new file mode 100644 index 000000000000..0454ffc1d364 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/memory.json @@ -0,0 +1,58 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS", + "PublicDescription": "Counts memory accesses issued by the CPU load store unit, where those accesses are issued due to load or store operations. This event counts memory accesses no matter whether the data is received from any level of cache hierarchy or external memory. If memory accesses are broken up into smaller transactions than what were specified in the load or store instructions, then the event counts those smaller memory transactions." + }, + { + "ArchStdEvent": "MEMORY_ERROR", + "PublicDescription": "Counts any detected correctable or uncorrectable physical memory errors (ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (including data and tag rams). Any detected memory error (from either a speculative and abandoned access, or an architecturally executed access) is counted. Note that errors are only detected when the actual protected memory is accessed by an operation." + }, + { + "ArchStdEvent": "REMOTE_ACCESS", + "PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mesh in the system. If the CHI bus response back to the core indicates that the data source is from another chip (mesh), then the counter is updated. If no data is returned, even if the system snoops another chip/mesh, then the counter is not updated." + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + "PublicDescription": "Counts memory accesses issued by the CPU due to load operations. The event counts any memory load access, no matter whether the data is received from any level of cache hierarchy or external memory. The event also counts atomic load operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions." + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + "PublicDescription": "Counts memory accesses issued by the CPU due to store operations. The event counts any memory store access, no matter whether the data is located in any level of cache or external memory. The event also counts atomic load and store operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions." + }, + { + "ArchStdEvent": "LDST_ALIGN_LAT", + "PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred additional latency, due to the alignment of the address and the size of data being accessed, which results in store crossing a single cache line." + }, + { + "ArchStdEvent": "LD_ALIGN_LAT", + "PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed, which results in load crossing a single cache line." + }, + { + "ArchStdEvent": "ST_ALIGN_LAT", + "PublicDescription": "Counts the number of memory write access in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed incurred additional latency." + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED", + "PublicDescription": "Counts the number of memory read and write accesses counted by MEM_ACCESS that are tag checked by the Memory Tagging Extension (MTE). This event is implemented as the sum of MEM_ACCESS_CHECKED_RD and MEM_ACCESS_CHECKED_WR" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_RD", + "PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by the Memory Tagging Extension (MTE)." + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_WR", + "PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by the Memory Tagging Extension (MTE)." + }, + { + "ArchStdEvent": "INST_FETCH_PERCYC", + "PublicDescription": "Counts number of instruction fetches outstanding per cycle, which will provide an average latency of instruction fetch." + }, + { + "ArchStdEvent": "MEM_ACCESS_RD_PERCYC", + "PublicDescription": "Counts the number of outstanding loads or memory read accesses per cycle." + }, + { + "ArchStdEvent": "INST_FETCH", + "PublicDescription": "Counts Instruction memory accesses that the PE makes." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json new file mode 100644 index 000000000000..4a671f55eaf3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json @@ -0,0 +1,457 @@ +[ + { + "ArchStdEvent": "backend_bound" + }, + { + "MetricName": "backend_busy_bound", + "MetricExpr": "STALL_BACKEND_BUSY / STALL_BACKEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to issue queues being full to accept operations for execution.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_cache_l1d_bound", + "MetricExpr": "STALL_BACKEND_L1D / (STALL_BACKEND_L1D + STALL_BACKEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by level 1 data cache misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_cache_l2d_bound", + "MetricExpr": "STALL_BACKEND_MEM / (STALL_BACKEND_L1D + STALL_BACKEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by level 2 data cache misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_core_bound", + "MetricExpr": "STALL_BACKEND_CPUBOUND / STALL_BACKEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend core resource constraints not related to instruction fetch latency issues caused by memory access components.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_core_rename_bound", + "MetricExpr": "STALL_BACKEND_RENAME / STALL_BACKEND_CPUBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend as the rename unit registers are unavailable.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_bound", + "MetricExpr": "STALL_BACKEND_MEMBOUND / STALL_BACKEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend core resource constraints related to memory access latency issues caused by memory access components.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_cache_bound", + "MetricExpr": "(STALL_BACKEND_L1D + STALL_BACKEND_MEM) / STALL_BACKEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory latency issues caused by data cache misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_store_bound", + "MetricExpr": "STALL_BACKEND_ST / STALL_BACKEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory write pending caused by stores stalled in the pre-commit stage.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_mem_tlb_bound", + "MetricExpr": "STALL_BACKEND_TLB / STALL_BACKEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by data TLB misses.", + "MetricGroup": "Topdown_Backend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "backend_stalled_cycles", + "MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "ArchStdEvent": "bad_speculation", + "MetricExpr": "(1 - STALL_SLOT / (10 * CPU_CYCLES)) * (1 - OP_RETIRED / OP_SPEC) * 100 + STALL_FRONTEND_FLUSH / CPU_CYCLES * 100" + }, + { + "MetricName": "barrier_percentage", + "MetricExpr": "(ISB_SPEC + DSB_SPEC + DMB_SPEC) / INST_SPEC * 100", + "BriefDescription": "This metric measures instruction and data barrier operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "branch_direct_ratio", + "MetricExpr": "BR_IMMED_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of direct branches retired to the total number of branches architecturally executed.", + "MetricGroup": "Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "branch_indirect_ratio", + "MetricExpr": "BR_IND_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of indirect branches retired, including function returns, to the total number of branches architecturally executed.", + "MetricGroup": "Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "branch_misprediction_ratio", + "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.", + "MetricGroup": "Miss_Ratio;Branch_Effectiveness", + "ScaleUnit": "100percent of branches" + }, + { + "MetricName": "branch_mpki", + "MetricExpr": "BR_MIS_PRED_RETIRED / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.", + "MetricGroup": "MPKI;Branch_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "branch_percentage", + "MetricExpr": "(BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC * 100", + "BriefDescription": "This metric measures branch operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "branch_return_ratio", + "MetricExpr": "BR_RETURN_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of branches retired that are function returns to the total number of branches architecturally executed.", + "MetricGroup": "Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "crypto_percentage", + "MetricExpr": "CRYPTO_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "dtlb_mpki", + "MetricExpr": "DTLB_WALK / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "dtlb_walk_ratio", + "MetricExpr": "DTLB_WALK / L1D_TLB", + "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "fp16_percentage", + "MetricExpr": "FP_HP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures half-precision floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "FP_Precision_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "fp32_percentage", + "MetricExpr": "FP_SP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures single-precision floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "FP_Precision_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "fp64_percentage", + "MetricExpr": "FP_DP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures double-precision floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "FP_Precision_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "fp_ops_per_cycle", + "MetricExpr": "(FP_SCALE_OPS_SPEC + FP_FIXED_OPS_SPEC) / CPU_CYCLES", + "BriefDescription": "This metric measures floating point operations per cycle in any precision performed by any instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.", + "MetricGroup": "FP_Arithmetic_Intensity", + "ScaleUnit": "1operations per cycle" + }, + { + "ArchStdEvent": "frontend_bound", + "MetricExpr": "(STALL_SLOT_FRONTEND / (10 * CPU_CYCLES) - STALL_FRONTEND_FLUSH / CPU_CYCLES) * 100" + }, + { + "MetricName": "frontend_cache_l1i_bound", + "MetricExpr": "STALL_FRONTEND_L1I / (STALL_FRONTEND_L1I + STALL_FRONTEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory access latency issues caused by level 1 instruction cache misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_cache_l2i_bound", + "MetricExpr": "STALL_FRONTEND_MEM / (STALL_FRONTEND_L1I + STALL_FRONTEND_MEM) * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory access latency issues caused by level 2 instruction cache misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_core_bound", + "MetricExpr": "STALL_FRONTEND_CPUBOUND / STALL_FRONTEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to frontend core resource constraints not related to instruction fetch latency issues caused by memory access components.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_core_flow_bound", + "MetricExpr": "STALL_FRONTEND_FLOW / STALL_FRONTEND_CPUBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend as the decode unit is awaiting input from the branch prediction unit.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_core_flush_bound", + "MetricExpr": "STALL_FRONTEND_FLUSH / STALL_FRONTEND_CPUBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend as the processor is recovering from a pipeline flush caused by bad speculation or other machine resteers.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_mem_bound", + "MetricExpr": "STALL_FRONTEND_MEMBOUND / STALL_FRONTEND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to frontend core resource constraints related to the instruction fetch latency issues caused by memory access components.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_mem_cache_bound", + "MetricExpr": "(STALL_FRONTEND_L1I + STALL_FRONTEND_MEM) / STALL_FRONTEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to instruction fetch latency issues caused by instruction cache misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_mem_tlb_bound", + "MetricExpr": "STALL_FRONTEND_TLB / STALL_FRONTEND_MEMBOUND * 100", + "BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to instruction fetch latency issues caused by instruction TLB misses.", + "MetricGroup": "Topdown_Frontend", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "frontend_stalled_cycles", + "MetricExpr": "STALL_FRONTEND / CPU_CYCLES * 100", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "integer_dp_percentage", + "MetricExpr": "DP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "ipc", + "MetricExpr": "INST_RETIRED / CPU_CYCLES", + "BriefDescription": "This metric measures the number of instructions retired per cycle.", + "MetricGroup": "General", + "ScaleUnit": "1per cycle" + }, + { + "MetricName": "itlb_mpki", + "MetricExpr": "ITLB_WALK / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "itlb_walk_ratio", + "MetricExpr": "ITLB_WALK / L1I_TLB", + "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1d_cache_miss_ratio", + "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", + "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", + "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l1d_cache_mpki", + "MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1D_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1d_tlb_miss_ratio", + "MetricExpr": "L1D_TLB_REFILL / L1D_TLB", + "BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1d_tlb_mpki", + "MetricExpr": "L1D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_cache_miss_ratio", + "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", + "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", + "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l1i_cache_mpki", + "MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1I_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_tlb_miss_ratio", + "MetricExpr": "L1I_TLB_REFILL / L1I_TLB", + "BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1i_tlb_mpki", + "MetricExpr": "L1I_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_cache_miss_ratio", + "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", + "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l2_cache_mpki", + "MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "MPKI;L2_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_tlb_miss_ratio", + "MetricExpr": "L2D_TLB_REFILL / L2D_TLB", + "BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l2_tlb_mpki", + "MetricExpr": "L2D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "ll_cache_read_hit_ratio", + "MetricExpr": "(LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD", + "BriefDescription": "This metric measures the ratio of last level cache read accesses hit in the cache to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", + "MetricGroup": "LL_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "ll_cache_read_miss_ratio", + "MetricExpr": "LL_CACHE_MISS_RD / LL_CACHE_RD", + "BriefDescription": "This metric measures the ratio of last level cache read accesses missed to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", + "MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "ll_cache_read_mpki", + "MetricExpr": "LL_CACHE_MISS_RD / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of last level cache read accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;LL_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "load_percentage", + "MetricExpr": "LD_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "nonsve_fp_ops_per_cycle", + "MetricExpr": "FP_FIXED_OPS_SPEC / CPU_CYCLES", + "BriefDescription": "This metric measures floating point operations per cycle in any precision performed by an instruction that is not an SVE instruction. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.", + "MetricGroup": "FP_Arithmetic_Intensity", + "ScaleUnit": "1operations per cycle" + }, + { + "ArchStdEvent": "retiring" + }, + { + "MetricName": "scalar_fp_percentage", + "MetricExpr": "VFP_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "simd_percentage", + "MetricExpr": "ASE_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "store_percentage", + "MetricExpr": "ST_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_all_percentage", + "MetricExpr": "SVE_INST_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations, including loads and stores, as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_fp_ops_per_cycle", + "MetricExpr": "FP_SCALE_OPS_SPEC / CPU_CYCLES", + "BriefDescription": "This metric measures floating point operations per cycle in any precision performed by SVE instructions. Operations are counted by computation and by vector lanes, fused computations such as multiply-add count as twice per vector lane for example.", + "MetricGroup": "FP_Arithmetic_Intensity", + "ScaleUnit": "1operations per cycle" + }, + { + "MetricName": "sve_predicate_empty_percentage", + "MetricExpr": "SVE_PRED_EMPTY_SPEC / SVE_PRED_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with no active predicates as a percentage of sve predicated operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_predicate_full_percentage", + "MetricExpr": "SVE_PRED_FULL_SPEC / SVE_PRED_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with all active predicates as a percentage of sve predicated operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_predicate_partial_percentage", + "MetricExpr": "SVE_PRED_PARTIAL_SPEC / SVE_PRED_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with at least one active predicates as a percentage of sve predicated operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "sve_predicate_percentage", + "MetricExpr": "SVE_PRED_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operations with predicates as a percentage of operations speculatively executed.", + "MetricGroup": "SVE_Effectiveness", + "ScaleUnit": "1percent of operations" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/retired.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/retired.json new file mode 100644 index 000000000000..04617c399dda --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/retired.json @@ -0,0 +1,98 @@ +[ + { + "ArchStdEvent": "SW_INCR", + "PublicDescription": "Counts software writes to the PMSWINC_EL0 (software PMU increment) register. The PMSWINC_EL0 register is a manually updated counter for use by application software.\n\nThis event could be used to measure any user program event, such as accesses to a particular data structure (by writing to the PMSWINC_EL0 register each time the data structure is accessed).\n\nTo use the PMSWINC_EL0 register and event, developers must insert instructions that write to the PMSWINC_EL0 register into the source code.\n\nSince the SW_INCR event records writes to the PMSWINC_EL0 register, there is no need to do a read/increment/write sequence to the PMSWINC_EL0 register." + }, + { + "ArchStdEvent": "INST_RETIRED", + "PublicDescription": "Counts instructions that have been architecturally executed." + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED", + "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR_EL1 register, which usually contain the kernel PID and can be output with hardware trace." + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches." + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED", + "PublicDescription": "Counts architecturally executed procedure returns." + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED", + "PublicDescription": "Counts architectural writes to TTBR0/1_EL1. If virtualization host extensions are enabled (by setting the HCR_EL2.E2H bit to 1), then accesses to TTBR0/1_EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers are typically updated when the kernel is swapping user-space threads or applications." + }, + { + "ArchStdEvent": "BR_RETIRED", + "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted. Note that exception generating instructions, exception return instructions and context synchronization instructions are not counted." + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED", + "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "OP_RETIRED", + "PublicDescription": "Counts micro-operations that are architecturally executed. This is a count of number of micro-operations retired from the commit queue in a single cycle." + }, + { + "ArchStdEvent": "BR_INDNR_TAKEN_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were taken." + }, + { + "ArchStdEvent": "BR_IMMED_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches that were correctly predicted." + }, + { + "ArchStdEvent": "BR_IMMED_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed direct branches that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_IND_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were correctly predicted." + }, + { + "ArchStdEvent": "BR_IND_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches including procedure returns that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_RETURN_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed procedure returns that were correctly predicted." + }, + { + "ArchStdEvent": "BR_RETURN_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed procedure returns that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_INDNR_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were correctly predicted." + }, + { + "ArchStdEvent": "BR_INDNR_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches excluding procedure returns that were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "BR_TAKEN_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed branches that were taken and were correctly predicted." + }, + { + "ArchStdEvent": "BR_TAKEN_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed branches that were taken and were mispredicted causing a pipeline flush." + }, + { + "ArchStdEvent": "BR_SKIP_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed branches that were not taken and were correctly predicted." + }, + { + "ArchStdEvent": "BR_SKIP_MIS_PRED_RETIRED", + "PublicDescription": "Counts architecturally executed branches that were not taken and were mispredicted causing a pipeline flush." + }, + { + "ArchStdEvent": "BR_PRED_RETIRED", + "PublicDescription": "Counts branch instructions counted by BR_RETIRED which were correctly predicted." + }, + { + "ArchStdEvent": "BR_IND_RETIRED", + "PublicDescription": "Counts architecturally executed indirect branches including procedure returns." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/spe.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/spe.json new file mode 100644 index 000000000000..ca0217fa4681 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/spe.json @@ -0,0 +1,42 @@ +[ + { + "ArchStdEvent": "SAMPLE_POP", + "PublicDescription": "Counts statistical profiling sample population, the count of all operations that could be sampled but may or may not be chosen for sampling." + }, + { + "ArchStdEvent": "SAMPLE_FEED", + "PublicDescription": "Counts statistical profiling samples taken for sampling." + }, + { + "ArchStdEvent": "SAMPLE_FILTRATE", + "PublicDescription": "Counts statistical profiling samples taken which are not removed by filtering." + }, + { + "ArchStdEvent": "SAMPLE_COLLISION", + "PublicDescription": "Counts statistical profiling samples that have collided with a previous sample and so therefore not taken." + }, + { + "ArchStdEvent": "SAMPLE_FEED_BR", + "PublicDescription": "Counts statistical profiling samples taken which are branches." + }, + { + "ArchStdEvent": "SAMPLE_FEED_LD", + "PublicDescription": "Counts statistical profiling samples taken which are loads or load atomic operations." + }, + { + "ArchStdEvent": "SAMPLE_FEED_ST", + "PublicDescription": "Counts statistical profiling samples taken which are stores or store atomic operations." + }, + { + "ArchStdEvent": "SAMPLE_FEED_OP", + "PublicDescription": "Counts statistical profiling samples taken which are matching any operation type filters supported." + }, + { + "ArchStdEvent": "SAMPLE_FEED_EVENT", + "PublicDescription": "Counts statistical profiling samples taken which are matching event packet filter constraints." + }, + { + "ArchStdEvent": "SAMPLE_FEED_LAT", + "PublicDescription": "Counts statistical profiling samples taken which are exceeding minimum latency set by operation latency filter constraints." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/spec_operation.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/spec_operation.json new file mode 100644 index 000000000000..7d7359402e9e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/spec_operation.json @@ -0,0 +1,126 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED", + "PublicDescription": "Counts branches which are speculatively executed and mispredicted." + }, + { + "ArchStdEvent": "BR_PRED", + "PublicDescription": "Counts all speculatively executed branches." + }, + { + "ArchStdEvent": "INST_SPEC", + "PublicDescription": "Counts operations that have been speculatively executed." + }, + { + "ArchStdEvent": "OP_SPEC", + "PublicDescription": "Counts micro-operations speculatively executed. This is the count of the number of micro-operations dispatched in a cycle." + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC", + "PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses. The event does not count preload operations (PLD, PLI)." + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC", + "PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses." + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC", + "PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses." + }, + { + "ArchStdEvent": "LDREX_SPEC", + "PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. For example: LDREX, LDX" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed and have successfully completed the store operation." + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed and have not successfully completed the store operation." + }, + { + "ArchStdEvent": "STREX_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed." + }, + { + "ArchStdEvent": "LD_SPEC", + "PublicDescription": "Counts speculatively executed load operations including Single Instruction Multiple Data (SIMD) load operations." + }, + { + "ArchStdEvent": "ST_SPEC", + "PublicDescription": "Counts speculatively executed store operations including Single Instruction Multiple Data (SIMD) store operations." + }, + { + "ArchStdEvent": "LDST_SPEC", + "PublicDescription": "Counts load and store operations that have been speculatively executed." + }, + { + "ArchStdEvent": "DP_SPEC", + "PublicDescription": "Counts speculatively executed logical or arithmetic instructions such as MOV/MVN operations." + }, + { + "ArchStdEvent": "ASE_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD operations excluding load, store and move micro-operations that move data to or from SIMD (vector) registers." + }, + { + "ArchStdEvent": "VFP_SPEC", + "PublicDescription": "Counts speculatively executed floating point operations. This event does not count operations that move data to or from floating point (vector) registers." + }, + { + "ArchStdEvent": "PC_WRITE_SPEC", + "PublicDescription": "Counts speculatively executed operations which cause software changes of the PC. Those operations include all taken branch operations." + }, + { + "ArchStdEvent": "CRYPTO_SPEC", + "PublicDescription": "Counts speculatively executed cryptographic operations except for PMULL and VMULL operations." + }, + { + "ArchStdEvent": "BR_IMMED_SPEC", + "PublicDescription": "Counts direct branch operations which are speculatively executed." + }, + { + "ArchStdEvent": "BR_RETURN_SPEC", + "PublicDescription": "Counts procedure return operations (RET, RETAA and RETAB) which are speculatively executed." + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC", + "PublicDescription": "Counts indirect branch operations including procedure returns, which are speculatively executed. This includes operations that force a software change of the PC, other than exception-generating operations and direct branch instructions. Some examples of the instructions counted by this event include BR Xn, RET, etc..." + }, + { + "ArchStdEvent": "ISB_SPEC", + "PublicDescription": "Counts ISB operations that are executed." + }, + { + "ArchStdEvent": "DSB_SPEC", + "PublicDescription": "Counts DSB operations that are speculatively issued to Load/Store unit in the CPU." + }, + { + "ArchStdEvent": "DMB_SPEC", + "PublicDescription": "Counts DMB operations that are speculatively issued to the Load/Store unit in the CPU. This event does not count implied barriers from load acquire/store release operations." + }, + { + "ArchStdEvent": "RC_LD_SPEC", + "PublicDescription": "Counts any load acquire operations that are speculatively executed. For example: LDAR, LDARH, LDARB" + }, + { + "ArchStdEvent": "RC_ST_SPEC", + "PublicDescription": "Counts any store release operations that are speculatively executed. For example: STLR, STLRH, STLRB" + }, + { + "ArchStdEvent": "SIMD_INST_SPEC", + "PublicDescription": "Counts speculatively executed operations that are SIMD or SVE vector operations or Advanced SIMD non-scalar operations." + }, + { + "ArchStdEvent": "ASE_INST_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD operations." + }, + { + "ArchStdEvent": "INT_SPEC", + "PublicDescription": "Counts speculatively executed integer arithmetic operations." + }, + { + "ArchStdEvent": "PRF_SPEC", + "PublicDescription": "Counts speculatively executed operations that prefetch memory. For example: Scalar: PRFM, SVE: PRFB, PRFD, PRFH, or PRFW." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/stall.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/stall.json new file mode 100644 index 000000000000..cafa73508db6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/stall.json @@ -0,0 +1,124 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND", + "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. STALL_FRONTEND_SLOTS counts SLOTS during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL_BACKEND", + "PublicDescription": "Counts cycles whenever the rename unit is unable to send any micro-operations to the backend of the pipeline because of backend resource constraints. Backend resource constraints can include issue stage fullness, execution stage fullness, or other internal pipeline resource fullness. All the backend slots were empty during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL", + "PublicDescription": "Counts cycles when no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). This event is the sum of STALL_FRONTEND and STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND", + "PublicDescription": "Counts slots per cycle in which no operations are sent from the rename unit to the backend due to backend resource constraints. STALL_BACKEND counts during the cycle when STALL_SLOT_BACKEND counts at least 1." + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND", + "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend due to frontend resource constraints." + }, + { + "ArchStdEvent": "STALL_SLOT", + "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). STALL_SLOT is the sum of STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND." + }, + { + "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the simple integer issue queues are full to take any operations for execution.", + "EventCode": "0x15C", + "EventName": "DISPATCH_STALL_IQ_SX", + "BriefDescription": "Dispatch stalled due to IQ full,SX" + }, + { + "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the complex integer issue queues are full and can not take any operations for execution.", + "EventCode": "0x15D", + "EventName": "DISPATCH_STALL_IQ_MX", + "BriefDescription": "Dispatch stalled due to IQ full,MX" + }, + { + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations\nbecause the load/store issue queues are full and can not take any operations for execution.", + "EventCode": "0x15E", + "EventName": "DISPATCH_STALL_IQ_LS", + "BriefDescription": "Dispatch stalled due to IQ full,LS" + }, + { + "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the vector issue queues are full and can not take any operations for execution.", + "EventCode": "0x15F", + "EventName": "DISPATCH_STALL_IQ_VX", + "BriefDescription": "Dispatch stalled due to IQ full,VX" + }, + { + "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the commit queue is full and can not take any operations for execution.", + "EventCode": "0x160", + "EventName": "DISPATCH_STALL_MCQ", + "BriefDescription": "Dispatch stalled due to MCQ full" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM", + "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the last level core cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_MEMBOUND", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the memory resources." + }, + { + "ArchStdEvent": "STALL_FRONTEND_L1I", + "PublicDescription": "Counts cycles when the frontend is stalled because there is an instruction fetch request pending in the level 1 instruction cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_MEM", + "PublicDescription": "Counts cycles when the frontend is stalled because there is an instruction fetch request pending in the last level core cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_TLB", + "PublicDescription": "Counts when the frontend is stalled on any TLB misses being handled. This event also counts the TLB accesses made by hardware prefetches." + }, + { + "ArchStdEvent": "STALL_FRONTEND_CPUBOUND", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the CPU resources excluding memory resources." + }, + { + "ArchStdEvent": "STALL_FRONTEND_FLOW", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the branch prediction unit." + }, + { + "ArchStdEvent": "STALL_FRONTEND_FLUSH", + "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage as the frontend is recovering from a machine flush or resteer. Example scenarios that cause a flush include branch mispredictions, taken exceptions, micro-architectural flush etc." + }, + { + "ArchStdEvent": "STALL_BACKEND_MEMBOUND", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to resource constraints in the memory resources." + }, + { + "ArchStdEvent": "STALL_BACKEND_L1D", + "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the level 1 data cache." + }, + { + "ArchStdEvent": "STALL_BACKEND_L2D", + "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the level 2 data cache." + }, + { + "ArchStdEvent": "STALL_BACKEND_TLB", + "PublicDescription": "Counts cycles when the backend is stalled on any demand TLB misses being handled." + }, + { + "ArchStdEvent": "STALL_BACKEND_ST", + "PublicDescription": "Counts cycles when the backend is stalled and there is a store that has not reached the pre-commit stage." + }, + { + "ArchStdEvent": "STALL_BACKEND_CPUBOUND", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to any resource constraints in the CPU excluding memory resources." + }, + { + "ArchStdEvent": "STALL_BACKEND_BUSY", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations because the issue queues are full to take any operations for execution." + }, + { + "ArchStdEvent": "STALL_BACKEND_ILOCK", + "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to resource constraints imposed by input dependency." + }, + { + "ArchStdEvent": "STALL_BACKEND_RENAME", + "PublicDescription": "Counts cycles when backend is stalled even when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/sve.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/sve.json new file mode 100644 index 000000000000..51dab48cb2ba --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/sve.json @@ -0,0 +1,50 @@ +[ + { + "ArchStdEvent": "SVE_INST_SPEC", + "PublicDescription": "Counts speculatively executed operations that are SVE operations." + }, + { + "ArchStdEvent": "SVE_PRED_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations." + }, + { + "ArchStdEvent": "SVE_PRED_EMPTY_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with no active predicate elements." + }, + { + "ArchStdEvent": "SVE_PRED_FULL_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with all predicate elements active." + }, + { + "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with at least one but not all active predicate elements." + }, + { + "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC", + "PublicDescription": "Counts speculatively executed predicated SVE operations with at least one non active predicate elements." + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC", + "PublicDescription": "Counts speculatively executed SVE first fault or non-fault load operations." + }, + { + "ArchStdEvent": "SVE_LDFF_FAULT_SPEC", + "PublicDescription": "Counts speculatively executed SVE first fault or non-fault load operations that clear at least one bit in the FFR." + }, + { + "ArchStdEvent": "ASE_SVE_INT8_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type an 8-bit integer." + }, + { + "ArchStdEvent": "ASE_SVE_INT16_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type a 16-bit integer." + }, + { + "ArchStdEvent": "ASE_SVE_INT32_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type a 32-bit integer." + }, + { + "ArchStdEvent": "ASE_SVE_INT64_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with the largest data type a 64-bit integer." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/tlb.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/tlb.json new file mode 100644 index 000000000000..41c5472c1def --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/tlb.json @@ -0,0 +1,138 @@ +[ + { + "ArchStdEvent": "L1I_TLB_REFILL", + "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL", + "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction." + }, + { + "ArchStdEvent": "L1D_TLB", + "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1I_TLB", + "PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This event counts both demand accesses and prefetch or preload generated accesses." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL", + "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches." + }, + { + "ArchStdEvent": "L2D_TLB", + "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK", + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + "PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an Address Translation (AT) instruction." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + "PublicDescription": "Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count with an access from an Address Translation (AT) instruction." + }, + { + "ArchStdEvent": "L1D_TLB_RD", + "PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1D_TLB_WR", + "PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD", + "PublicDescription": "Counts level 2 TLB refills caused by memory read operations from both data and instruction fetch except for those caused by TLB maintenance operations or hardware prefetches." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR", + "PublicDescription": "Counts level 2 TLB refills caused by memory write operations from both data and instruction fetch except for those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "L2D_TLB_RD", + "PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data and instruction fetch except for those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "L2D_TLB_WR", + "PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data and instruction fetch except for those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK_PERCYC", + "PublicDescription": "Counts the number of data translation table walks in progress per cycle." + }, + { + "ArchStdEvent": "ITLB_WALK_PERCYC", + "PublicDescription": "Counts the number of instruction translation table walks in progress per cycle." + }, + { + "ArchStdEvent": "L1D_TLB_RW", + "PublicDescription": "Counts level 1 data TLB demand accesses caused by memory read or write operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1I_TLB_RD", + "PublicDescription": "Counts level 1 instruction TLB demand accesses whether the access hits or misses in the TLB." + }, + { + "ArchStdEvent": "L1D_TLB_PRFM", + "PublicDescription": "Counts level 1 data TLB accesses generated by software prefetch or preload memory accesses. Load or store instructions can be broken into multiple memory operations. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1I_TLB_PRFM", + "PublicDescription": "Counts level 1 instruction TLB accesses generated by software preload or prefetch instructions. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_HWUPD", + "PublicDescription": "Counts number of memory accesses triggered by a data translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers." + }, + { + "ArchStdEvent": "ITLB_HWUPD", + "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing an update of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD." + }, + { + "ArchStdEvent": "DTLB_STEP", + "PublicDescription": "Counts number of memory accesses triggered by a demand data translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts accesses triggered by software preloads, but not accesses triggered by hardware prefetchers." + }, + { + "ArchStdEvent": "ITLB_STEP", + "PublicDescription": "Counts number of memory accesses triggered by an instruction translation table walk and performing a read of a translation table entry. Memory accesses are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD." + }, + { + "ArchStdEvent": "DTLB_WALK_LARGE", + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_BLOCK is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK_LARGE", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a large page. The set of large pages is defined as all pages with a final size higher than or equal to 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. In this family, this is equal to ITLB_WALK_BLOCK event. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK_SMALL", + "PublicDescription": "Counts number of data translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. If DTLB_WALK_PAGE event is implemented, then it is an alias for this event in this family. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK_SMALL", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and yielding a small page. The set of small pages is defined as all pages with a final size lower than 2MB. Translation table walks that end up taking a translation fault are not counted, as the page size would be undefined in that case. In this family, this is equal to ITLB_WALK_PAGE event. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK_RW", + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK_RD", + "PublicDescription": "Counts number of demand instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK_PRFM", + "PublicDescription": "Counts number of software prefetches or preloads generated data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK_PRFM", + "PublicDescription": "Counts number of software prefetches or preloads generated instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json index 492083b99256..e40be37addf8 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -228,6 +228,16 @@ "BriefDescription": "Attributable Level 1 instruction TLB access" }, { + "EventCode": "0x27", + "EventName": "L2I_CACHE", + "BriefDescription": "Level 2 instruction cache access" + }, + { + "EventCode": "0x28", + "EventName": "L2I_CACHE_REFILL", + "BriefDescription": "Level 2 instruction cache refill" + }, + { "PublicDescription": "Attributable Level 3 data cache allocation without refill", "EventCode": "0x29", "EventName": "L3D_CACHE_ALLOCATE", @@ -276,6 +286,16 @@ "BriefDescription": "Access to another socket in a multi-socket system" }, { + "EventCode": "0x32", + "EventName": "LL_CACHE", + "BriefDescription": "Last level cache access" + }, + { + "EventCode": "0x33", + "EventName": "LL_CACHE_MISS", + "BriefDescription": "Last level cache miss" + }, + { "PublicDescription": "Access to data TLB causes a translation table walk", "EventCode": "0x34", "EventName": "DTLB_WALK", @@ -396,6 +416,11 @@ "BriefDescription": "Level 2 data cache long-latency read miss" }, { + "EventCode": "0x400A", + "EventName": "L2I_CACHE_LMISS", + "BriefDescription": "Level 2 instruction cache long-latency miss" + }, + { "PublicDescription": "Level 3 data cache long-latency read miss. The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element. The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache.", "EventCode": "0x400B", "EventName": "L3D_CACHE_LMISS_RD", @@ -522,6 +547,11 @@ "BriefDescription": "Instruction architecturally executed, SVE." }, { + "EventCode": "0x8004", + "EventName": "SIMD_INST_SPEC", + "BriefDescription": "Operation speculatively executed, SIMD" + }, + { "PublicDescription": "ASE operations speculatively executed", "EventCode": "0x8005", "EventName": "ASE_INST_SPEC", @@ -534,6 +564,11 @@ "BriefDescription": "SVE operations speculatively executed" }, { + "EventCode": "0x8007", + "EventName": "ASE_SVE_INST_SPEC", + "BriefDescription": "Operation speculatively executed, Advanced SIMD or SVE." + }, + { "PublicDescription": "Microarchitectural operation, Operations speculatively executed.", "EventCode": "0x8008", "EventName": "UOP_SPEC", @@ -552,48 +587,393 @@ "BriefDescription": "Floating-point Operations speculatively executed." }, { + "EventCode": "0x8011", + "EventName": "ASE_FP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD." + }, + { + "EventCode": "0x8012", + "EventName": "SVE_FP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE." + }, + { + "EventCode": "0x8013", + "EventName": "ASE_SVE_FP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE." + }, + { "PublicDescription": "Floating-point half-precision operations speculatively executed", "EventCode": "0x8014", "EventName": "FP_HP_SPEC", "BriefDescription": "Floating-point half-precision operations speculatively executed" }, { + "EventCode": "0x8015", + "EventName": "ASE_FP_HP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD half precision." + }, + { + "EventCode": "0x8016", + "EventName": "SVE_FP_HP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE half precision." + }, + { + "EventCode": "0x8017", + "EventName": "ASE_SVE_FP_HP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE half precision." + }, + { "PublicDescription": "Floating-point single-precision operations speculatively executed", "EventCode": "0x8018", "EventName": "FP_SP_SPEC", "BriefDescription": "Floating-point single-precision operations speculatively executed" }, { + "EventCode": "0x8019", + "EventName": "ASE_FP_SP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD single precision." + }, + { + "EventCode": "0x801A", + "EventName": "SVE_FP_SP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE single precision." + }, + { + "EventCode": "0x801B", + "EventName": "ASE_SVE_FP_SP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE single precision." + }, + { "PublicDescription": "Floating-point double-precision operations speculatively executed", "EventCode": "0x801C", "EventName": "FP_DP_SPEC", "BriefDescription": "Floating-point double-precision operations speculatively executed" }, { + "EventCode": "0x801D", + "EventName": "ASE_FP_DP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD double precision." + }, + { + "EventCode": "0x801E", + "EventName": "SVE_FP_DP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE double precision." + }, + { + "EventCode": "0x801F", + "EventName": "ASE_SVE_FP_DP_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE double precision." + }, + { + "EventCode": "0x8020", + "EventName": "FP_DIV_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, divide." + }, + { + "EventCode": "0x8021", + "EventName": "ASE_FP_DIV_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD divide." + }, + { + "EventCode": "0x8022", + "EventName": "SVE_FP_DIV_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE divide." + }, + { + "EventCode": "0x8023", + "EventName": "ASE_SVE_FP_DIV_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE divide." + }, + { + "EventCode": "0x8024", + "EventName": "FP_SQRT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, square root." + }, + { + "EventCode": "0x8025", + "EventName": "ASE_FP_SQRT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD square root." + }, + { + "EventCode": "0x8026", + "EventName": "SVE_FP_SQRT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE square root." + }, + { + "EventCode": "0x8027", + "EventName": "ASE_SVE_FP_SQRT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE square-root." + }, + { "PublicDescription": "Floating-point FMA Operations speculatively executed.", "EventCode": "0x8028", "EventName": "FP_FMA_SPEC", "BriefDescription": "Floating-point FMA Operations speculatively executed." }, { + "EventCode": "0x8029", + "EventName": "ASE_FP_FMA_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD FMA." + }, + { + "EventCode": "0x802A", + "EventName": "SVE_FP_FMA_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE FMA." + }, + { + "EventCode": "0x802B", + "EventName": "ASE_SVE_FP_FMA_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE FMA." + }, + { + "EventCode": "0x802C", + "EventName": "FP_MUL_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, multiply." + }, + { + "EventCode": "0x802D", + "EventName": "ASE_FP_MUL_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD multiply." + }, + { + "EventCode": "0x802E", + "EventName": "SVE_FP_MUL_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE multiply." + }, + { + "EventCode": "0x802F", + "EventName": "ASE_SVE_FP_MUL_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE multiply." + }, + { + "EventCode": "0x8030", + "EventName": "FP_ADDSUB_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, add or subtract." + }, + { + "EventCode": "0x8031", + "EventName": "ASE_FP_ADDSUB_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD add or subtract." + }, + { + "EventCode": "0x8032", + "EventName": "SVE_FP_ADDSUB_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE add or subtract." + }, + { + "EventCode": "0x8033", + "EventName": "ASE_SVE_FP_ADDSUB_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE add or subtract." + }, + { "PublicDescription": "Floating-point reciprocal estimate Operations speculatively executed.", "EventCode": "0x8034", "EventName": "FP_RECPE_SPEC", "BriefDescription": "Floating-point reciprocal estimate Operations speculatively executed." }, { + "EventCode": "0x8035", + "EventName": "ASE_FP_RECPE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD reciprocal estimate." + }, + { + "EventCode": "0x8036", + "EventName": "SVE_FP_RECPE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE reciprocal estimate." + }, + { + "EventCode": "0x8037", + "EventName": "ASE_SVE_FP_RECPE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE reciprocal estimate." + }, + { "PublicDescription": "floating-point convert Operations speculatively executed.", "EventCode": "0x8038", "EventName": "FP_CVT_SPEC", "BriefDescription": "floating-point convert Operations speculatively executed." }, { + "EventCode": "0x8039", + "EventName": "ASE_FP_CVT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD convert." + }, + { + "EventCode": "0x803A", + "EventName": "SVE_FP_CVT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE convert." + }, + { + "EventCode": "0x803B", + "EventName": "ASE_SVE_FP_CVT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE convert." + }, + { + "EventCode": "0x803C", + "EventName": "SVE_FP_AREDUCE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE accumulating reduction." + }, + { + "EventCode": "0x803D", + "EventName": "ASE_FP_PREDUCE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD pairwise add step." + }, + { + "EventCode": "0x803E", + "EventName": "SVE_FP_VREDUCE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, SVE vector reduction." + }, + { + "EventCode": "0x803F", + "EventName": "ASE_SVE_FP_VREDUCE_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE vector reduction." + }, + { + "EventCode": "0x8040", + "EventName": "INT_SPEC", + "BriefDescription": "Integer Operation speculatively executed." + }, + { + "EventCode": "0x8041", + "EventName": "ASE_INT_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD." + }, + { + "EventCode": "0x8042", + "EventName": "SVE_INT_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE." + }, + { "PublicDescription": "Advanced SIMD and SVE integer Operations speculatively executed.", "EventCode": "0x8043", "EventName": "ASE_SVE_INT_SPEC", "BriefDescription": "Advanced SIMD and SVE integer Operations speculatively executed." }, { + "EventCode": "0x8044", + "EventName": "INT_DIV_SPEC", + "BriefDescription": "Integer Operation speculatively executed, divide." + }, + { + "EventCode": "0x8045", + "EventName": "INT_DIV64_SPEC", + "BriefDescription": "Integer Operation speculatively executed, 64-bit divide." + }, + { + "EventCode": "0x8046", + "EventName": "SVE_INT_DIV_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE divide." + }, + { + "EventCode": "0x8047", + "EventName": "SVE_INT_DIV64_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE 64-bit divide." + }, + { + "EventCode": "0x8048", + "EventName": "INT_MUL_SPEC", + "BriefDescription": "Integer Operation speculatively executed, multiply." + }, + { + "EventCode": "0x8049", + "EventName": "ASE_INT_MUL_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD multiply." + }, + { + "EventCode": "0x804A", + "EventName": "SVE_INT_MUL_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE multiply." + }, + { + "EventCode": "0x804B", + "EventName": "ASE_SVE_INT_MUL_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE multiply." + }, + { + "EventCode": "0x804C", + "EventName": "INT_MUL64_SPEC", + "BriefDescription": "Integer Operation speculatively executed, 64\u00d764 multiply." + }, + { + "EventCode": "0x804D", + "EventName": "SVE_INT_MUL64_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE 64\u00d764 multiply." + }, + { + "EventCode": "0x804E", + "EventName": "INT_MULH64_SPEC", + "BriefDescription": "Integer Operation speculatively executed, 64\u00d764 multiply returning high part." + }, + { + "EventCode": "0x804F", + "EventName": "SVE_INT_MULH64_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE 64\u00d764 multiply high part." + }, + { + "EventCode": "0x8058", + "EventName": "NONFP_SPEC", + "BriefDescription": "Non-floating-point Operation speculatively executed." + }, + { + "EventCode": "0x8059", + "EventName": "ASE_NONFP_SPEC", + "BriefDescription": "Non-floating-point Operation speculatively executed, Advanced SIMD." + }, + { + "EventCode": "0x805A", + "EventName": "SVE_NONFP_SPEC", + "BriefDescription": "Non-floating-point Operation speculatively executed, SVE." + }, + { + "EventCode": "0x805B", + "EventName": "ASE_SVE_NONFP_SPEC", + "BriefDescription": "Non-floating-point Operation speculatively executed, Advanced SIMD or SVE." + }, + { + "EventCode": "0x805D", + "EventName": "ASE_INT_VREDUCE_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD reduction." + }, + { + "EventCode": "0x805E", + "EventName": "SVE_INT_VREDUCE_SPEC", + "BriefDescription": "Integer Operation speculatively executed, SVE reduction." + }, + { + "EventCode": "0x805F", + "EventName": "ASE_SVE_INT_VREDUCE_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE reduction." + }, + { + "EventCode": "0x8060", + "EventName": "SVE_PERM_SPEC", + "BriefDescription": "Operation speculatively executed, SVE permute." + }, + { + "EventCode": "0x8065", + "EventName": "SVE_XPIPE_Z2R_SPEC", + "BriefDescription": "Operation speculatively executed, SVE vector to scalar cross-pipe." + }, + { + "EventCode": "0x8066", + "EventName": "SVE_XPIPE_R2Z_SPEC", + "BriefDescription": "Operation speculatively executed, SVE scalar to vector cross-pipe." + }, + { + "EventCode": "0x8068", + "EventName": "SVE_PGEN_SPEC", + "BriefDescription": "Operation speculatively executed, SVE predicate generating." + }, + { + "EventCode": "0x8069", + "EventName": "SVE_PGEN_FLG_SPEC", + "BriefDescription": "Operation speculatively executed, SVE predicate flag setting." + }, + { + "EventCode": "0x806D", + "EventName": "SVE_PPERM_SPEC", + "BriefDescription": "Operation speculatively executed, SVE predicate permute." + }, + { "PublicDescription": "SVE predicated Operations speculatively executed.", "EventCode": "0x8074", "EventName": "SVE_PRED_SPEC", @@ -630,6 +1010,16 @@ "BriefDescription": "SVE MOVPRFX Operations speculatively executed." }, { + "EventCode": "0x807D", + "EventName": "SVE_MOVPRFX_Z_SPEC", + "BriefDescription": "Operation speculatively executed, SVE MOVPRFX zeroing predication." + }, + { + "EventCode": "0x807E", + "EventName": "SVE_MOVPRFX_M_SPEC", + "BriefDescription": "Operation speculatively executed, SVE MOVPRFX merging predication." + }, + { "PublicDescription": "SVE MOVPRFX unfused Operations speculatively executed.", "EventCode": "0x807F", "EventName": "SVE_MOVPRFX_U_SPEC", @@ -696,6 +1086,16 @@ "BriefDescription": "SVE contiguous prefetch element Operations speculatively executed." }, { + "EventCode": "0x80A1", + "EventName": "SVE_LDNT_CONTIG_SPEC", + "BriefDescription": "Operation speculatively executed, SVE non-temporal contiguous load element." + }, + { + "EventCode": "0x80A2", + "EventName": "SVE_STNT_CONTIG_SPEC", + "BriefDescription": "Operation speculatively executed, SVE non-temporal contiguous store element." + }, + { "PublicDescription": "Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed.", "EventCode": "0x80A5", "EventName": "ASE_SVE_LD_MULTI_SPEC", @@ -786,6 +1186,16 @@ "BriefDescription": "Non-scalable double-precision floating-point element Operations speculatively executed." }, { + "EventCode": "0x80C8", + "EventName": "INT_SCALE_OPS_SPEC", + "BriefDescription": "Scalable integer element arithmetic operations Speculatively executed." + }, + { + "EventCode": "0x80C9", + "EventName": "INT_FIXED_OPS_SPEC", + "BriefDescription": "Non-scalable integer element arithmetic operations Speculatively executed." + }, + { "PublicDescription": "Advanced SIMD and SVE 8-bit integer operations speculatively executed", "EventCode": "0x80E3", "EventName": "ASE_SVE_INT8_SPEC", @@ -808,5 +1218,620 @@ "EventCode": "0x80EF", "EventName": "ASE_SVE_INT64_SPEC", "BriefDescription": "Advanced SIMD and SVE 64-bit integer operations speculatively executed" + }, + { + "EventCode": "0x80F3", + "EventName": "ASE_SVE_FP_DOT_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE dot-product." + }, + { + "EventCode": "0x80F7", + "EventName": "ASE_SVE_FP_MMLA_SPEC", + "BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE matrix multiply." + }, + { + "EventCode": "0x80FB", + "EventName": "ASE_SVE_INT_DOT_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE dot-product." + }, + { + "EventCode": "0x80FF", + "EventName": "ASE_SVE_INT_MMLA_SPEC", + "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE matrix multiply." + }, + { + "EventCode": "0x8108", + "EventName": "BR_IMMED_TAKEN_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, immediate, taken" + }, + { + "EventCode": "0x810C", + "EventName": "BR_INDNR_TAKEN_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, indirect excluding procedure return, taken" + }, + { + "EventCode": "0x8110", + "EventName": "BR_IMMED_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted immediate" + }, + { + "EventCode": "0x8111", + "EventName": "BR_IMMED_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted immediate" + }, + { + "EventCode": "0x8112", + "EventName": "BR_IND_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted indirect" + }, + { + "EventCode": "0x8113", + "EventName": "BR_IND_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted indirect" + }, + { + "EventCode": "0x8114", + "EventName": "BR_RETURN_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted procedure return" + }, + { + "EventCode": "0x8115", + "EventName": "BR_RETURN_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted procedure return" + }, + { + "EventCode": "0x8116", + "EventName": "BR_INDNR_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted indirect excluding procedure return" + }, + { + "EventCode": "0x8117", + "EventName": "BR_INDNR_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted indirect excluding procedure return" + }, + { + "EventCode": "0x8118", + "EventName": "BR_TAKEN_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted branch, taken" + }, + { + "EventCode": "0x8119", + "EventName": "BR_TAKEN_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted branch, taken" + }, + { + "EventCode": "0x811A", + "EventName": "BR_SKIP_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted branch, not taken" + }, + { + "EventCode": "0x811B", + "EventName": "BR_SKIP_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted branch, not taken" + }, + { + "EventCode": "0x811C", + "EventName": "BR_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted branch" + }, + { + "EventCode": "0x811D", + "EventName": "BR_IND_RETIRED", + "BriefDescription": "Instruction architecturally executed, indirect branch" + }, + { + "EventCode": "0x811F", + "EventName": "BRB_FILTRATE", + "BriefDescription": "Branch Record captured" + }, + { + "EventCode": "0x8120", + "EventName": "INST_FETCH_PERCYC", + "BriefDescription": "Event in progress, INST FETCH" + }, + { + "EventCode": "0x8121", + "EventName": "MEM_ACCESS_RD_PERCYC", + "BriefDescription": "Event in progress, MEM ACCESS RD" + }, + { + "EventCode": "0x8124", + "EventName": "INST_FETCH", + "BriefDescription": "Instruction memory access" + }, + { + "EventCode": "0x8128", + "EventName": "DTLB_WALK_PERCYC", + "BriefDescription": "Data translation table walks in progress." + }, + { + "EventCode": "0x8129", + "EventName": "ITLB_WALK_PERCYC", + "BriefDescription": "Instruction translation table walks in progress." + }, + { + "EventCode": "0x812A", + "EventName": "SAMPLE_FEED_BR", + "BriefDescription": "Statisical Profiling sample taken, branch" + }, + { + "EventCode": "0x812B", + "EventName": "SAMPLE_FEED_LD", + "BriefDescription": "Statisical Profiling sample taken, load" + }, + { + "EventCode": "0x812C", + "EventName": "SAMPLE_FEED_ST", + "BriefDescription": "Statisical Profiling sample taken, store" + }, + { + "EventCode": "0x812D", + "EventName": "SAMPLE_FEED_OP", + "BriefDescription": "Statisical Profiling sample taken, matching operation type" + }, + { + "EventCode": "0x812E", + "EventName": "SAMPLE_FEED_EVENT", + "BriefDescription": "Statisical Profiling sample taken, matching events" + }, + { + "EventCode": "0x812F", + "EventName": "SAMPLE_FEED_LAT", + "BriefDescription": "Statisical Profiling sample taken, exceeding minimum latency" + }, + { + "EventCode": "0x8130", + "EventName": "L1D_TLB_RW", + "BriefDescription": "Level 1 data TLB demand access" + }, + { + "EventCode": "0x8131", + "EventName": "L1I_TLB_RD", + "BriefDescription": "Level 1 instruction TLB demand access" + }, + { + "EventCode": "0x8132", + "EventName": "L1D_TLB_PRFM", + "BriefDescription": "Level 1 data TLB software preload" + }, + { + "EventCode": "0x8133", + "EventName": "L1I_TLB_PRFM", + "BriefDescription": "Level 1 instruction TLB software preload" + }, + { + "EventCode": "0x8134", + "EventName": "DTLB_HWUPD", + "BriefDescription": "Data TLB hardware update of translation table" + }, + { + "EventCode": "0x8135", + "EventName": "ITLB_HWUPD", + "BriefDescription": "Instruction TLB hardware update of translation table" + }, + { + "EventCode": "0x8136", + "EventName": "DTLB_STEP", + "BriefDescription": "Data TLB translation table walk, step." + }, + { + "EventCode": "0x8137", + "EventName": "ITLB_STEP", + "BriefDescription": "Instruction TLB translation table walk, step." + }, + { + "EventCode": "0x8138", + "EventName": "DTLB_WALK_LARGE", + "BriefDescription": "Data TLB large page translation table walk." + }, + { + "EventCode": "0x8139", + "EventName": "ITLB_WALK_LARGE", + "BriefDescription": "Instruction TLB large page translation table walk." + }, + { + "EventCode": "0x813A", + "EventName": "DTLB_WALK_SMALL", + "BriefDescription": "Data TLB small page translation table walk." + }, + { + "EventCode": "0x813B", + "EventName": "ITLB_WALK_SMALL", + "BriefDescription": "Instruction TLB small page translation table walk." + }, + { + "EventCode": "0x813C", + "EventName": "DTLB_WALK_RW", + "BriefDescription": "Data TLB demand access with at least one translation table walk" + }, + { + "EventCode": "0x813D", + "EventName": "ITLB_WALK_RD", + "BriefDescription": "Instruction TLB demand access with at least one translation table walk" + }, + { + "EventCode": "0x813E", + "EventName": "DTLB_WALK_PRFM", + "BriefDescription": "Data TLB software preload access with at least one translation table walk" + }, + { + "EventCode": "0x813F", + "EventName": "ITLB_WALK_PRFM", + "BriefDescription": "Instruction TLB software preload access with at least one translation table walk" + }, + { + "EventCode": "0x8140", + "EventName": "L1D_CACHE_RW", + "BriefDescription": "Level 1 data cache demand access" + }, + { + "EventCode": "0x8141", + "EventName": "L1I_CACHE_RD", + "BriefDescription": "Level 1 instruction cache demand fetch" + }, + { + "EventCode": "0x8142", + "EventName": "L1D_CACHE_PRFM", + "BriefDescription": "Level 1 data cache software preload" + }, + { + "EventCode": "0x8143", + "EventName": "L1I_CACHE_PRFM", + "BriefDescription": "Level 1 instruction cache software preload" + }, + { + "EventCode": "0x8144", + "EventName": "L1D_CACHE_MISS", + "BriefDescription": "Level 1 data cache demand access miss." + }, + { + "EventCode": "0x8145", + "EventName": "L1I_CACHE_HWPRF", + "BriefDescription": "Level 1 instruction cache hardware prefetch." + }, + { + "EventCode": "0x8146", + "EventName": "L1D_CACHE_REFILL_PRFM", + "BriefDescription": "Level 1 data cache refill, software preload" + }, + { + "EventCode": "0x8147", + "EventName": "L1I_CACHE_REFILL_PRFM", + "BriefDescription": "Level 1 instruction cache refill, software preload" + }, + { + "EventCode": "0x8148", + "EventName": "L2D_CACHE_RW", + "BriefDescription": "Level 2 data cache demand access" + }, + { + "EventCode": "0x8149", + "EventName": "L2I_CACHE_RD", + "BriefDescription": "Level 2 instruction cache demand fetch" + }, + { + "EventCode": "0x814A", + "EventName": "L2D_CACHE_PRFM", + "BriefDescription": "Level 2 data cache software preload" + }, + { + "EventCode": "0x814C", + "EventName": "L2D_CACHE_MISS", + "BriefDescription": "Level 2 data cache demand access miss." + }, + { + "EventCode": "0x814E", + "EventName": "L2D_CACHE_REFILL_PRFM", + "BriefDescription": "Level 2 data cache refill, software preload" + }, + { + "EventCode": "0x8152", + "EventName": "L3D_CACHE_MISS", + "BriefDescription": "Level 3 data cache demand access miss" + }, + { + "EventCode": "0x8154", + "EventName": "L1D_CACHE_HWPRF", + "BriefDescription": "Level 1 data cache hardware prefetch." + }, + { + "EventCode": "0x8155", + "EventName": "L2D_CACHE_HWPRF", + "BriefDescription": "Level 2 data cache hardware prefetch." + }, + { + "EventCode": "0x8158", + "EventName": "STALL_FRONTEND_MEMBOUND", + "BriefDescription": "Frontend stall cycles, memory bound." + }, + { + "EventCode": "0x8159", + "EventName": "STALL_FRONTEND_L1I", + "BriefDescription": "Frontend stall cycles, level 1 instruction cache." + }, + { + "EventCode": "0x815A", + "EventName": "STALL_FRONTEND_L2I", + "BriefDescription": "Frontend stall cycles, level 2 instruction cache." + }, + { + "EventCode": "0x815B", + "EventName": "STALL_FRONTEND_MEM", + "BriefDescription": "Frontend stall cycles, last level PE cache or memory." + }, + { + "EventCode": "0x815C", + "EventName": "STALL_FRONTEND_TLB", + "BriefDescription": "Frontend stall cycles, TLB." + }, + { + "EventCode": "0x8160", + "EventName": "STALL_FRONTEND_CPUBOUND", + "BriefDescription": "Frontend stall cycles, processor bound." + }, + { + "EventCode": "0x8161", + "EventName": "STALL_FRONTEND_FLOW", + "BriefDescription": "Frontend stall cycles, flow control." + }, + { + "EventCode": "0x8162", + "EventName": "STALL_FRONTEND_FLUSH", + "BriefDescription": "Frontend stall cycles, flush recovery." + }, + { + "EventCode": "0x8163", + "EventName": "STALL_FRONTEND_RENAME", + "BriefDescription": "Frontend stall cycles, rename full." + }, + { + "EventCode": "0x8164", + "EventName": "STALL_BACKEND_MEMBOUND", + "BriefDescription": "Backend stall cycles, memory bound." + }, + { + "EventCode": "0x8165", + "EventName": "STALL_BACKEND_L1D", + "BriefDescription": "Backend stall cycles, level 1 data cache." + }, + { + "EventCode": "0x8166", + "EventName": "STALL_BACKEND_L2D", + "BriefDescription": "Backend stall cycles, level 2 data cache." + }, + { + "EventCode": "0x8167", + "EventName": "STALL_BACKEND_TLB", + "BriefDescription": "Backend stall cycles, TLB." + }, + { + "EventCode": "0x8168", + "EventName": "STALL_BACKEND_ST", + "BriefDescription": "Backend stall cycles, store." + }, + { + "EventCode": "0x816A", + "EventName": "STALL_BACKEND_CPUBOUND", + "BriefDescription": "Backend stall cycles, processor bound." + }, + { + "EventCode": "0x816B", + "EventName": "STALL_BACKEND_BUSY", + "BriefDescription": "Backend stall cycles, backend busy." + }, + { + "EventCode": "0x816C", + "EventName": "STALL_BACKEND_ILOCK", + "BriefDescription": "Backend stall cycles, input dependency." + }, + { + "EventCode": "0x816D", + "EventName": "STALL_BACKEND_RENAME", + "BriefDescription": "Backend stall cycles, rename full." + }, + { + "EventCode": "0x816E", + "EventName": "STALL_BACKEND_ATOMIC", + "BriefDescription": "Backend stall cycles, atomic operation." + }, + { + "EventCode": "0x816F", + "EventName": "STALL_BACKEND_MEMCPYSET", + "BriefDescription": "Backend stall cycles, Memory Copy or Set operation." + }, + { + "EventCode": "0x8171", + "EventName": "CAS_NEAR_PASS", + "BriefDescription": "Atomic memory Operation speculatively executed, Compare and Swap pass" + }, + { + "EventCode": "0x8172", + "EventName": "CAS_NEAR_SPEC", + "BriefDescription": "Atomic memory Operation speculatively executed, Compare and Swap near" + }, + { + "EventCode": "0x8173", + "EventName": "CAS_FAR_SPEC", + "BriefDescription": "Atomic memory Operation speculatively executed, Compare and Swap far" + }, + { + "EventCode": "0x8186", + "EventName": "UOP_RETIRED", + "BriefDescription": "Micro-operation architecturally executed." + }, + { + "EventCode": "0x8188", + "EventName": "DTLB_WALK_BLOCK", + "BriefDescription": "Data TLB block translation table walk." + }, + { + "EventCode": "0x8189", + "EventName": "ITLB_WALK_BLOCK", + "BriefDescription": "Instruction TLB block translation table walk." + }, + { + "EventCode": "0x818A", + "EventName": "DTLB_WALK_PAGE", + "BriefDescription": "Data TLB page translation table walk." + }, + { + "EventCode": "0x818B", + "EventName": "ITLB_WALK_PAGE", + "BriefDescription": "Instruction TLB page translation table walk." + }, + { + "EventCode": "0x81B8", + "EventName": "L1I_CACHE_REFILL_HWPRF", + "BriefDescription": "Level 1 instruction cache refill, hardware prefetch." + }, + { + "EventCode": "0x81BC", + "EventName": "L1D_CACHE_REFILL_HWPRF", + "BriefDescription": "Level 1 data cache refill, hardware prefetch." + }, + { + "EventCode": "0x81BD", + "EventName": "L2D_CACHE_REFILL_HWPRF", + "BriefDescription": "Level 2 data cache refill, hardware prefetch." + }, + { + "EventCode": "0x81C0", + "EventName": "L1I_CACHE_HIT_RD", + "BriefDescription": "Level 1 instruction cache demand fetch hit." + }, + { + "EventCode": "0x81C4", + "EventName": "L1D_CACHE_HIT_RD", + "BriefDescription": "Level 1 data cache demand access hit, read." + }, + { + "EventCode": "0x81C5", + "EventName": "L2D_CACHE_HIT_RD", + "BriefDescription": "Level 2 data cache demand access hit, read." + }, + { + "EventCode": "0x81C8", + "EventName": "L1D_CACHE_HIT_WR", + "BriefDescription": "Level 1 data cache demand access hit, write." + }, + { + "EventCode": "0x81C9", + "EventName": "L2D_CACHE_HIT_WR", + "BriefDescription": "Level 2 data cache demand access hit, write." + }, + { + "EventCode": "0x81D0", + "EventName": "L1I_CACHE_HIT_RD_FPRFM", + "BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by software preload" + }, + { + "EventCode": "0x81E0", + "EventName": "L1I_CACHE_HIT_RD_FHWPRF", + "BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by hardware prefetcher" + }, + { + "EventCode": "0x8200", + "EventName": "L1I_CACHE_HIT", + "BriefDescription": "Level 1 instruction cache hit." + }, + { + "EventCode": "0x8204", + "EventName": "L1D_CACHE_HIT", + "BriefDescription": "Level 1 data cache hit." + }, + { + "EventCode": "0x8205", + "EventName": "L2D_CACHE_HIT", + "BriefDescription": "Level 2 data cache hit." + }, + { + "EventCode": "0x8208", + "EventName": "L1I_CACHE_HIT_PRFM", + "BriefDescription": "Level 1 instruction cache software preload hit" + }, + { + "EventCode": "0x8240", + "EventName": "L1I_LFB_HIT_RD", + "BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer hit." + }, + { + "EventCode": "0x8244", + "EventName": "L1D_LFB_HIT_RD", + "BriefDescription": "Level 1 data cache demand access line-fill buffer hit, read." + }, + { + "EventCode": "0x8245", + "EventName": "L2D_LFB_HIT_RD", + "BriefDescription": "Level 2 data cache demand access line-fill buffer hit, read." + }, + { + "EventCode": "0x8248", + "EventName": "L1D_LFB_HIT_WR", + "BriefDescription": "Level 1 data cache demand access line-fill buffer hit, write." + }, + { + "EventCode": "0x8249", + "EventName": "L2D_LFB_HIT_WR", + "BriefDescription": "Level 2 data cache demand access line-fill buffer hit, write." + }, + { + "EventCode": "0x8250", + "EventName": "L1I_LFB_HIT_RD_FPRFM", + "BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer first hit, recently fetched by software preload" + }, + { + "EventCode": "0x8260", + "EventName": "L1I_LFB_HIT_RD_FHWPRF", + "BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer first hit, recently fetched by hardware prefetcher" + }, + { + "EventCode": "0x8280", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "Level 1 instruction cache, preload or prefetch hit." + }, + { + "EventCode": "0x8284", + "EventName": "L1D_CACHE_PRF", + "BriefDescription": "Level 1 data cache, preload or prefetch hit." + }, + { + "EventCode": "0x8285", + "EventName": "L2D_CACHE_PRF", + "BriefDescription": "Level 2 data cache, preload or prefetch hit." + }, + { + "EventCode": "0x8288", + "EventName": "L1I_CACHE_REFILL_PRF", + "BriefDescription": "Level 1 instruction cache refill, preload or prefetch hit." + }, + { + "EventCode": "0x828C", + "EventName": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "Level 1 data cache refill, preload or prefetch hit." + }, + { + "EventCode": "0x828D", + "EventName": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "Level 2 data cache refill, preload or prefetch hit." + }, + { + "EventCode": "0x829A", + "EventName": "LL_CACHE_REFILL", + "BriefDescription": "Last level cache refill" + }, + { + "EventCode": "0x8320", + "EventName": "L1D_CACHE_REFILL_PERCYC", + "BriefDescription": "Level 1 data or unified cache refills in progress." + }, + { + "EventCode": "0x8321", + "EventName": "L2D_CACHE_REFILL_PERCYC", + "BriefDescription": "Level 2 data or unified cache refills in progress." + }, + { + "EventCode": "0x8324", + "EventName": "L1I_CACHE_REFILL_PERCYC", + "BriefDescription": "Level 1 instruction or unified cache refills in progress." } ] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx91/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx91/sys/ddrc.json new file mode 100644 index 000000000000..74ac12660a29 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx91/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx91_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx91" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx91/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx91/sys/metrics.json new file mode 100644 index 000000000000..f0c5911eb2d0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx91/sys/metrics.json @@ -0,0 +1,26 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr4 evk board", + "MetricName": "imx91_bandwidth_usage.lpddr4", + "MetricExpr": "(((( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8 ) + (( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32 )) / duration_time) / (2400 * 1000000 * 2)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx91" + }, + { + "BriefDescription": "bytes all masters read from ddr", + "MetricName": "imx91_ddr_read.all", + "MetricExpr": "( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx91" + }, + { + "BriefDescription": "bytes all masters write to ddr", + "MetricName": "imx91_ddr_write.all", + "MetricExpr": "( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx91" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json new file mode 100644 index 000000000000..eeeae4d49fce --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx93_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx93" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json new file mode 100644 index 000000000000..4d2454ca1259 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json @@ -0,0 +1,26 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr4x evk board", + "MetricName": "imx93_bandwidth_usage.lpddr4x", + "MetricExpr": "(((( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8 ) + (( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32 )) / duration_time) / (3733 * 1000000 * 2)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx93" + }, + { + "BriefDescription": "bytes all masters read from ddr", + "MetricName": "imx93_ddr_read.all", + "MetricExpr": "( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx93" + }, + { + "BriefDescription": "bytes all masters write to ddr", + "MetricName": "imx93_ddr_write.all", + "MetricExpr": "( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx93" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json new file mode 100644 index 000000000000..4dc9d2968bdc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx95_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json new file mode 100644 index 000000000000..45a0d51dfb63 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json @@ -0,0 +1,882 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr5 evk board", + "MetricName": "imx95_bandwidth_usage.lpddr5", + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bandwidth usage for lpddr4x evk board", + "MetricName": "imx95_bandwidth_usage.lpddr4x", + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (4000 * 1000000 * 4)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters read from ddr", + "MetricName": "imx95_ddr_read.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters write to ddr", + "MetricName": "imx95_ddr_write.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 read from ddr", + "MetricName": "imx95_ddr_read.a55_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part1)", + "MetricName": "imx95_ddr_write.a55_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part2)", + "MetricName": "imx95_ddr_write.a55_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 read from ddr", + "MetricName": "imx95_ddr_read.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 write to ddr", + "MetricName": "imx95_ddr_write.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 read from ddr", + "MetricName": "imx95_ddr_read.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 write to ddr", + "MetricName": "imx95_ddr_write.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 read from ddr", + "MetricName": "imx95_ddr_read.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 write to ddr", + "MetricName": "imx95_ddr_write.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 read from ddr", + "MetricName": "imx95_ddr_read.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 write to ddr", + "MetricName": "imx95_ddr_write.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 read from ddr", + "MetricName": "imx95_ddr_read.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 write to ddr", + "MetricName": "imx95_ddr_write.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 read from ddr", + "MetricName": "imx95_ddr_read.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 write to ddr", + "MetricName": "imx95_ddr_write.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr", + "MetricName": "imx95_ddr_read.cortexa_dsu_l3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr", + "MetricName": "imx95_ddr_write.cortexa_dsu_l3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 read from ddr", + "MetricName": "imx95_ddr_read.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 write to ddr", + "MetricName": "imx95_ddr_write.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 read from ddr", + "MetricName": "imx95_ddr_read.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 write to ddr", + "MetricName": "imx95_ddr_write.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": 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"BriefDescription": "bytes of netc write to ddr", + "MetricName": "imx95_ddr_write.netc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of npu read from ddr", + "MetricName": "imx95_ddr_read.npu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of npu write to ddr", + "MetricName": "imx95_ddr_write.npu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of gpu read from ddr", + "MetricName": "imx95_ddr_read.gpu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 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"BriefDescription": "bytes of pcie3 write to ddr", + "MetricName": "imx95_ddr_write.pcie3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie4 read from ddr", + "MetricName": "imx95_ddr_read.pcie4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie4 write to ddr", + "MetricName": "imx95_ddr_write.pcie4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb1 read from ddr", + "MetricName": "imx95_ddr_read.usb1", + "MetricExpr": "( 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"BriefDescription": "bytes of vpu codec primary bus read from ddr", + "MetricName": "imx95_ddr_read.vpu_primy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec primary bus write to ddr", + "MetricName": "imx95_ddr_write.vpu_primy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus read from ddr", + "MetricName": "imx95_ddr_read.vpu_secndy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", + "MetricName": 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"9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd read from ddr", + "MetricName": "imx95_ddr_read.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd write to ddr", + "MetricName": "imx95_ddr_write.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules read from ddr", + "MetricName": "imx95_ddr_read.camera_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.camera_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.camera_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", + "MetricName": "imx95_ddr_write.camera_all_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer0 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer0 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer1 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer1 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer2 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x310@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer2 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x310@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer3 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x320@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer3 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x320@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer4 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x330@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer4 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x330@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer5 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x340@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer5 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x340@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter read from ddr", + "MetricName": "imx95_ddr_read.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x350@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter write to ddr", + "MetricName": "imx95_ddr_write.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x350@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer read from ddr", + "MetricName": "imx95_ddr_read.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x360@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer write to ddr", + "MetricName": "imx95_ddr_write.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x360@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules read from ddr", + "MetricName": "imx95_ddr_read.disp_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.disp_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.disp_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json new file mode 100644 index 000000000000..52f5ca1482fe --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json @@ -0,0 +1,6 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_PRF", + "BriefDescription": "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json new file mode 100644 index 000000000000..24ff5d8dbb98 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json @@ -0,0 +1,122 @@ +[ + { + "EventCode": "0x0182", + "EventName": "LD_COMP_WAIT_L1_MISS", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access." + }, + { + "EventCode": "0x0183", + "EventName": "LD_COMP_WAIT_L1_MISS_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access." + }, + { + "EventCode": "0x0184", + "EventName": "LD_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access." + }, + { + "EventCode": "0x0185", + "EventName": "LD_COMP_WAIT_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access." + }, + { + "EventCode": "0x0186", + "EventName": "LD_COMP_WAIT_PFP_BUSY", + "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port." + }, + { + "EventCode": "0x0187", + "EventName": "LD_COMP_WAIT_PFP_BUSY_EX", + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation." + }, + { + "EventCode": "0x0188", + "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF", + "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction." + }, + { + "EventCode": "0x0189", + "EventName": "EU_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction." + }, + { + "EventCode": "0x018A", + "EventName": "FL_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction." + }, + { + "EventCode": "0x018B", + "EventName": "BR_COMP_WAIT", + "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction." + }, + { + "EventCode": "0x018C", + "EventName": "ROB_EMPTY", + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty." + }, + { + "EventCode": "0x018D", + "EventName": "ROB_EMPTY_STQ_BUSY", + "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full." + }, + { + "EventCode": "0x018E", + "EventName": "WFE_WFI_CYCLE", + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction." + }, + { + "EventCode": "0x018F", + "EventName": "RETENTION_CYCLE", + "BriefDescription": "This event counts every cycle that the instruction unit is halted by the RETENTION state." + }, + { + "EventCode": "0x0190", + "EventName": "_0INST_COMMIT", + "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only." + }, + { + "EventCode": "0x0191", + "EventName": "_1INST_COMMIT", + "BriefDescription": "This event counts every cycle that one instruction is committed." + }, + { + "EventCode": "0x0192", + "EventName": "_2INST_COMMIT", + "BriefDescription": "This event counts every cycle that two instructions are committed." + }, + { + "EventCode": "0x0193", + "EventName": "_3INST_COMMIT", + "BriefDescription": "This event counts every cycle that three instructions are committed." + }, + { + "EventCode": "0x0194", + "EventName": "_4INST_COMMIT", + "BriefDescription": "This event counts every cycle that four instructions are committed." + }, + { + "EventCode": "0x0195", + "EventName": "_5INST_COMMIT", + "BriefDescription": "This event counts every cycle that five instructions are committed." + }, + { + "EventCode": "0x0198", + "EventName": "UOP_ONLY_COMMIT", + "BriefDescription": "This event counts every cycle that only any micro-operations are committed." + }, + { + "EventCode": "0x0199", + "EventName": "SINGLE_MOVPRFX_COMMIT", + "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed." + }, + { + "EventCode": "0x019C", + "EventName": "LD_COMP_WAIT_L2_MISS", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache miss." + }, + { + "EventCode": "0x019D", + "EventName": "LD_COMP_WAIT_L2_MISS_EX", + "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache miss." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/energy.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/energy.json new file mode 100644 index 000000000000..b55173f71e42 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/energy.json @@ -0,0 +1,17 @@ +[ + { + "EventCode": "0x01F0", + "EventName": "EA_CORE", + "BriefDescription": "This event counts energy consumption of core." + }, + { + "EventCode": "0x03F0", + "EventName": "EA_L3", + "BriefDescription": "This event counts energy consumption of L3 cache." + }, + { + "EventCode": "0x03F1", + "EventName": "EA_LDO_LOSS", + "BriefDescription": "This event counts energy consumption of LDO loss." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json new file mode 100644 index 000000000000..f231712fe261 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json @@ -0,0 +1,42 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN", + "BriefDescription": "This event counts each exception taken." + }, + { + "ArchStdEvent": "EXC_RETURN", + "BriefDescription": "This event counts each executed exception return instruction." + }, + { + "ArchStdEvent": "EXC_UNDEF", + "BriefDescription": "This event counts only other synchronous exceptions that are taken locally." + }, + { + "ArchStdEvent": "EXC_SVC", + "BriefDescription": "This event counts only Supervisor Call exceptions that are taken locally." + }, + { + "ArchStdEvent": "EXC_PABORT", + "BriefDescription": "This event counts only Instruction Abort exceptions that are taken locally." + }, + { + "ArchStdEvent": "EXC_DABORT", + "BriefDescription": "This event counts only Data Abort or SError interrupt exceptions that are taken locally." + }, + { + "ArchStdEvent": "EXC_IRQ", + "BriefDescription": "This event counts only IRQ exceptions that are taken locally, including Virtual IRQ exceptions." + }, + { + "ArchStdEvent": "EXC_FIQ", + "BriefDescription": "This event counts only FIQ exceptions that are taken locally, including Virtual FIQ exceptions." + }, + { + "ArchStdEvent": "EXC_SMC", + "BriefDescription": "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception." + }, + { + "ArchStdEvent": "EXC_HVC", + "BriefDescription": "This event counts for both Hypervisor Call exceptions taken locally in the hypervisor and those taken as an exception from Non-secure EL1." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json new file mode 100644 index 000000000000..a3c368959199 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json @@ -0,0 +1,209 @@ +[ + { + "EventCode": "0x0105", + "EventName": "FP_MV_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point move operations." + }, + { + "EventCode": "0x0112", + "EventName": "FP_LD_SPEC", + "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers." + }, + { + "EventCode": "0x0113", + "EventName": "FP_ST_SPEC", + "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers." + }, + { + "ArchStdEvent": "ASE_FP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point operation." + }, + { + "ArchStdEvent": "SVE_FP_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point operations." + }, + { + "ArchStdEvent": "FP_HP_SPEC", + "BriefDescription": "This event counts architecturally executed half-precision floating-point operation." + }, + { + "ArchStdEvent": "ASE_FP_HP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD half-precision floating-point operation." + }, + { + "ArchStdEvent": "SVE_FP_HP_SPEC", + "BriefDescription": "This event counts architecturally executed SVE half-precision floating-point operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_HP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations." + }, + { + "ArchStdEvent": "FP_SP_SPEC", + "BriefDescription": "This event counts architecturally executed single-precision floating-point operation." + }, + { + "ArchStdEvent": "ASE_FP_SP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD single-precision floating-point operation." + }, + { + "ArchStdEvent": "SVE_FP_SP_SPEC", + "BriefDescription": "This event counts architecturally executed SVE single-precision floating-point operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_SP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations." + }, + { + "ArchStdEvent": "FP_DP_SPEC", + "BriefDescription": "This event counts architecturally executed double-precision floating-point operation." + }, + { + "ArchStdEvent": "ASE_FP_DP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD double-precision floating-point operation." + }, + { + "ArchStdEvent": "SVE_FP_DP_SPEC", + "BriefDescription": "This event counts architecturally executed SVE double-precision floating-point operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_DP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations." + }, + { + "ArchStdEvent": "FP_DIV_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point divide operation." + }, + { + "ArchStdEvent": "ASE_FP_DIV_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point divide operation." + }, + { + "ArchStdEvent": "SVE_FP_DIV_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point divide operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_DIV_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations." + }, + { + "ArchStdEvent": "FP_SQRT_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point square root operation." + }, + { + "ArchStdEvent": "ASE_FP_SQRT_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point square root operation." + }, + { + "ArchStdEvent": "SVE_FP_SQRT_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point square root operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_SQRT_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations." + }, + { + "ArchStdEvent": "ASE_FP_FMA_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point FMA operation." + }, + { + "ArchStdEvent": "SVE_FP_FMA_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point FMA operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_FMA_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations." + }, + { + "ArchStdEvent": "FP_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point multiply operations." + }, + { + "ArchStdEvent": "ASE_FP_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point multiply operation." + }, + { + "ArchStdEvent": "SVE_FP_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point multiply operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations." + }, + { + "ArchStdEvent": "FP_ADDSUB_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point add or subtract operations." + }, + { + "ArchStdEvent": "ASE_FP_ADDSUB_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point add or subtract operation." + }, + { + "ArchStdEvent": "SVE_FP_ADDSUB_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point add or subtract operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_ADDSUB_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations." + }, + { + "ArchStdEvent": "ASE_FP_RECPE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations." + }, + { + "ArchStdEvent": "SVE_FP_RECPE_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operations." + }, + { + "ArchStdEvent": "ASE_SVE_FP_RECPE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations." + }, + { + "ArchStdEvent": "ASE_FP_CVT_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point convert operation." + }, + { + "ArchStdEvent": "SVE_FP_CVT_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point convert operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_CVT_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations." + }, + { + "ArchStdEvent": "SVE_FP_AREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operations." + }, + { + "ArchStdEvent": "ASE_FP_PREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations." + }, + { + "ArchStdEvent": "SVE_FP_VREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed SVE floating-point vector reduction operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_VREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations." + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC." + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC." + }, + { + "ArchStdEvent": "ASE_SVE_FP_DOT_SPEC", + "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point dot-product operation." + }, + { + "ArchStdEvent": "ASE_SVE_FP_MMLA_SPEC", + "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point matrix multiply operation." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/gcycle.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/gcycle.json new file mode 100644 index 000000000000..b4ceddc0d25e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/gcycle.json @@ -0,0 +1,97 @@ +[ + { + "EventCode": "0x0880", + "EventName": "GCYCLES", + "BriefDescription": "This event counts the number of cycles at 100MHz." + }, + { + "EventCode": "0x0890", + "EventName": "FL0_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 0." + }, + { + "EventCode": "0x0891", + "EventName": "FL1_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 1." + }, + { + "EventCode": "0x0892", + "EventName": "FL2_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 2." + }, + { + "EventCode": "0x0893", + "EventName": "FL3_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 3." + }, + { + "EventCode": "0x0894", + "EventName": "FL4_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 4." + }, + { + "EventCode": "0x0895", + "EventName": "FL5_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 5." + }, + { + "EventCode": "0x0896", + "EventName": "FL6_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 6." + }, + { + "EventCode": "0x0897", + "EventName": "FL7_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 7." + }, + { + "EventCode": "0x0898", + "EventName": "FL8_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 8." + }, + { + "EventCode": "0x0899", + "EventName": "FL9_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 9." + }, + { + "EventCode": "0x089A", + "EventName": "FL10_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 10." + }, + { + "EventCode": "0x089B", + "EventName": "FL11_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 11." + }, + { + "EventCode": "0x089C", + "EventName": "FL12_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 12." + }, + { + "EventCode": "0x089D", + "EventName": "FL13_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 13." + }, + { + "EventCode": "0x089E", + "EventName": "FL14_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 14." + }, + { + "EventCode": "0x089F", + "EventName": "FL15_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 15." + }, + { + "EventCode": "0x08A0", + "EventName": "RETENTION_GCYCLES", + "BriefDescription": "This event counts the number of cycles where the measured core is staying in the RETENTION state." + }, + { + "EventCode": "0x08A1", + "EventName": "RETENTION_COUNT", + "BriefDescription": "This event counts the number of changes from the normal state to the RETENTION state." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/general.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/general.json new file mode 100644 index 000000000000..32f0fbfc4de4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/general.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES", + "BriefDescription": "This event counts every cycle." + }, + { + "ArchStdEvent": "CNT_CYCLES", + "BriefDescription": "This event counts the constant frequency cycles counter increments at a constant frequency equal to the rate of increment of the System counter." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/hwpf.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/hwpf.json new file mode 100644 index 000000000000..a784a032f353 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/hwpf.json @@ -0,0 +1,52 @@ +[ + { + "EventCode": "0x0230", + "EventName": "L1HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher." + }, + { + "EventCode": "0x0231", + "EventName": "L1HWPF_STRIDE_PF", + "BriefDescription": "This event counts stride prefetch requests to L1D cache generated by hardware prefetcher." + }, + { + "EventCode": "0x0232", + "EventName": "L1HWPF_PFTGT_PF", + "BriefDescription": "This event counts LDS prefetch requests to L1D cache generated by hardware prefetcher." + }, + { + "EventCode": "0x0234", + "EventName": "L2HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefetcher." + }, + { + "EventCode": "0x0235", + "EventName": "L2HWPF_STRIDE_PF", + "BriefDescription": "This event counts stride prefetch requests to L2 cache generated by hardware prefetcher." + }, + { + "EventCode": "0x0237", + "EventName": "L2HWPF_OTHER", + "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes." + }, + { + "EventCode": "0x0238", + "EventName": "L3HWPF_STREAM_PF", + "BriefDescription": "This event counts streaming prefetch requests to L3 cache generated by hardware prefetcher." + }, + { + "EventCode": "0x0239", + "EventName": "L3HWPF_STRIDE_PF", + "BriefDescription": "This event counts stride prefetch requests to L3 cache generated by hardware prefetcher." + }, + { + "EventCode": "0x023B", + "EventName": "L3HWPF_OTHER", + "BriefDescription": "This event counts prefetch requests to L3 cache generated by the other causes." + }, + { + "EventCode": "0x023C", + "EventName": "L1IHWPF_NEXTLINE_PF", + "BriefDescription": "This event counts next line's prefetch requests to L1I cache generated by hardware prefetcher." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json new file mode 100644 index 000000000000..b0818a2fedb0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json @@ -0,0 +1,113 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_REFILL", + "BriefDescription": "This event counts operations that cause a refill of the L1D cache. See L1D_CACHE_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1D_CACHE", + "BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See L1D_CACHE of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1D_CACHE_WB", + "BriefDescription": "This event counts every write-back of data from the L1D cache. See L1D_CACHE_WB of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD", + "BriefDescription": "This event counts operations that cause a refill of the L1D cache that incurs additional latency." + }, + { + "ArchStdEvent": "L1D_CACHE_RD", + "BriefDescription": "This event counts L1D CACHE caused by read access." + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + "BriefDescription": "This event counts L1D CACHE caused by write access." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access." + }, + { + "EventCode": "0x0200", + "EventName": "L1D_CACHE_DM", + "BriefDescription": "This event counts L1D_CACHE caused by demand access." + }, + { + "EventCode": "0x0201", + "EventName": "L1D_CACHE_DM_RD", + "BriefDescription": "This event counts L1D_CACHE caused by demand read access." + }, + { + "EventCode": "0x0202", + "EventName": "L1D_CACHE_DM_WR", + "BriefDescription": "This event counts L1D_CACHE caused by demand write access." + }, + { + "EventCode": "0x0208", + "EventName": "L1D_CACHE_REFILL_DM", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access." + }, + { + "EventCode": "0x0209", + "EventName": "L1D_CACHE_REFILL_DM_RD", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access." + }, + { + "EventCode": "0x020A", + "EventName": "L1D_CACHE_REFILL_DM_WR", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand write access." + }, + { + "EventCode": "0x020D", + "EventName": "L1D_CACHE_BTC", + "BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data cache, causing a coherence access to outside of the Level 1 caches of this PE." + }, + { + "ArchStdEvent": "L1D_CACHE_MISS", + "BriefDescription": "This event counts demand access that misses in the Level 1 data cache, causing an access to outside of the Level 1 caches of this PE." + }, + { + "ArchStdEvent": "L1D_CACHE_HWPRF", + "BriefDescription": "This event counts access counted by L1D_CACHE that is due to a hardware prefetch." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_CACHE_HIT_RD", + "BriefDescription": "This event counts demand read counted by L1D_CACHE_RD that hits in the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_CACHE_HIT_WR", + "BriefDescription": "This event counts demand write counted by L1D_CACHE_WR that hits in the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_CACHE_HIT", + "BriefDescription": "This event counts access counted by L1D_CACHE that hits in the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_LFB_HIT_RD", + "BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_LFB_HIT_WR", + "BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_WR that hits a cache line that is in the process of being loaded into the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_CACHE_PRF", + "BriefDescription": "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_PERCYC", + "BriefDescription": "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1i_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1i_cache.json new file mode 100644 index 000000000000..8680d8ec461d --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1i_cache.json @@ -0,0 +1,52 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL", + "BriefDescription": "This event counts operations that cause a refill of the L1I cache. See L1I_CACHE_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1I_CACHE", + "BriefDescription": "This event counts operations that cause a cache access to the L1I cache. See L1I_CACHE of ARMv9 Reference Manual for more information." + }, + { + "EventCode": "0x0207", + "EventName": "L1I_CACHE_DM_RD", + "BriefDescription": "This event counts L1I_CACHE caused by demand read access." + }, + { + "EventCode": "0x020F", + "EventName": "L1I_CACHE_REFILL_DM_RD", + "BriefDescription": "This event counts L1I_CACHE_REFILL caused by demand read access." + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS", + "BriefDescription": "This event counts operations that cause a refill of the L1I cache that incurs additional latency." + }, + { + "ArchStdEvent": "L1I_CACHE_HWPRF", + "BriefDescription": "This event counts access counted by L1I_CACHE that is due to a hardware prefetch." + }, + { + "ArchStdEvent": "L1I_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT_RD", + "BriefDescription": "This event counts demand fetch counted by L1I_CACHE_DM_RD that hits in the Level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_HIT", + "BriefDescription": "This event counts access counted by L1I_CACHE that hits in the Level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_LFB_HIT_RD", + "BriefDescription": "This event counts demand access counted by L1I_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_REFILL_PRF", + "BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache." + }, + { + "ArchStdEvent": "L1I_CACHE_REFILL_PERCYC", + "BriefDescription": "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json new file mode 100644 index 000000000000..9e092752e6db --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json @@ -0,0 +1,160 @@ +[ + { + "ArchStdEvent": "L2D_CACHE", + "BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L2D_CACHE of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL", + "BriefDescription": "This event counts operations that cause a refill of the L2 cache. See L2D_CACHE_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L2D_CACHE_WB", + "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace, non-temporal-store and DC ZVA." + }, + { + "ArchStdEvent": "L2I_TLB_REFILL", + "BriefDescription": "This event counts operations that cause a TLB refill of the L2I TLB. See L2I_TLB_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L2I_TLB", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_TLB of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + "BriefDescription": "This event counts L2D CACHE caused by read access." + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + "BriefDescription": "This event counts L2D CACHE caused by write access." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "BriefDescription": "This event counts L2D CACHE_REFILL caused by read access." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "BriefDescription": "This event counts L2D CACHE_REFILL caused by write access." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace." + }, + { + "EventCode": "0x0300", + "EventName": "L2D_CACHE_DM", + "BriefDescription": "This event counts L2D_CACHE caused by demand access." + }, + { + "EventCode": "0x0301", + "EventName": "L2D_CACHE_DM_RD", + "BriefDescription": "This event counts L2D_CACHE caused by demand read access." + }, + { + "EventCode": "0x0302", + "EventName": "L2D_CACHE_DM_WR", + "BriefDescription": "This event counts L2D_CACHE caused by demand write access." + }, + { + "EventCode": "0x0305", + "EventName": "L2D_CACHE_HWPRF_ADJACENT", + "BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch access." + }, + { + "EventCode": "0x0308", + "EventName": "L2D_CACHE_REFILL_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access." + }, + { + "EventCode": "0x0309", + "EventName": "L2D_CACHE_REFILL_DM_RD", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand read access." + }, + { + "EventCode": "0x030A", + "EventName": "L2D_CACHE_REFILL_DM_WR", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write access." + }, + { + "EventCode": "0x030B", + "EventName": "L2D_CACHE_REFILL_DM_WR_EXCL", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write exclusive access." + }, + { + "EventCode": "0x030C", + "EventName": "L2D_CACHE_REFILL_DM_WR_ATOM", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write atomic access." + }, + { + "EventCode": "0x030D", + "EventName": "L2D_CACHE_BTC", + "BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data and Level 2 caches, causing a coherence access to outside of the Level 1 and Level 2 caches of this PE." + }, + { + "EventCode": "0x03B0", + "EventName": "L2D_CACHE_WB_VICTIM_CLEAN", + "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace where the data is clean. In this case, the data will usually be written to L3 cache." + }, + { + "EventCode": "0x03B1", + "EventName": "L2D_CACHE_WB_NT", + "BriefDescription": "This event counts every write-back of data from the L2 cache caused by non-temporal-store." + }, + { + "EventCode": "0x03B2", + "EventName": "L2D_CACHE_WB_DCZVA", + "BriefDescription": "This event counts every write-back of data from the L2 cache caused by DC ZVA." + }, + { + "EventCode": "0x03B3", + "EventName": "L2D_CACHE_FB", + "BriefDescription": "This event counts every flush-back (drop) of data from the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD", + "BriefDescription": "This event counts operations that cause a refill of the L2D cache that incurs additional latency." + }, + { + "ArchStdEvent": "L2D_CACHE_MISS", + "BriefDescription": "This event counts demand access that misses in the Level 1 data and Level 2 caches, causing an access to outside of the Level 1 and Level 2 caches of this PE." + }, + { + "ArchStdEvent": "L2D_CACHE_HWPRF", + "BriefDescription": "This event counts access counted by L2D_CACHE that is due to a hardware prefetch." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_HWPRF", + "BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a refill of the Level 2 cache, or any Level 1 data and instruction cache of this PE, from outside of those caches." + }, + { + "ArchStdEvent": "L2D_CACHE_HIT_RD", + "BriefDescription": "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 data cache." + }, + { + "ArchStdEvent": "L2D_CACHE_HIT_WR", + "BriefDescription": "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 data cache." + }, + { + "ArchStdEvent": "L2D_CACHE_HIT", + "BriefDescription": "This event counts access counted by L2D_CACHE that hits in the Level 2 data cache." + }, + { + "ArchStdEvent": "L2D_LFB_HIT_RD", + "BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_RD that hits a recently fetched line in the Level 2 cache." + }, + { + "ArchStdEvent": "L2D_LFB_HIT_WR", + "BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_WR that hits a recently fetched line in the Level 2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_PRF", + "BriefDescription": "This event counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a refill of the Level 2 data cache from outside of the Level 1 data cache." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_PERCYC", + "BriefDescription": "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json new file mode 100644 index 000000000000..3f3e0d22ac68 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json @@ -0,0 +1,159 @@ +[ + { + "ArchStdEvent": "L3D_CACHE", + "BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as defined by the sum of L2D_CACHE_REFILL_L3D_CACHE and L2D_CACHE_WB_VICTIM_CLEAN events." + }, + { + "ArchStdEvent": "L3D_CACHE_RD", + "BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events." + }, + { + "EventCode": "0x0390", + "EventName": "L2D_CACHE_REFILL_L3D_CACHE", + "BriefDescription": "This event counts operations that cause a cache access to the L3 cache." + }, + { + "EventCode": "0x0391", + "EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access." + }, + { + "EventCode": "0x0392", + "EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_RD", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access." + }, + { + "EventCode": "0x0393", + "EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_WR", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access." + }, + { + "EventCode": "0x0394", + "EventName": "L2D_CACHE_REFILL_L3D_CACHE_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access." + }, + { + "EventCode": "0x0395", + "EventName": "L2D_CACHE_REFILL_L3D_CACHE_HWPRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access." + }, + { + "EventCode": "0x0396", + "EventName": "L2D_CACHE_REFILL_L3D_MISS", + "BriefDescription": "This event counts operations that cause a miss of the L3 cache." + }, + { + "EventCode": "0x0397", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access." + }, + { + "EventCode": "0x0398", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_RD", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access." + }, + { + "EventCode": "0x0399", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access." + }, + { + "EventCode": "0x039A", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access." + }, + { + "EventCode": "0x039B", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_HWPRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access." + }, + { + "EventCode": "0x039C", + "EventName": "L2D_CACHE_REFILL_L3D_HIT", + "BriefDescription": "This event counts operations that cause a hit of the L3 cache." + }, + { + "EventCode": "0x039D", + "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access." + }, + { + "EventCode": "0x039E", + "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_RD", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand read access." + }, + { + "EventCode": "0x039F", + "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_WR", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand write access." + }, + { + "EventCode": "0x03A0", + "EventName": "L2D_CACHE_REFILL_L3D_HIT_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access." + }, + { + "EventCode": "0x03A1", + "EventName": "L2D_CACHE_REFILL_L3D_HIT_HWPRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access." + }, + { + "EventCode": "0x03A2", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT", + "BriefDescription": "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer." + }, + { + "EventCode": "0x03A3", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access." + }, + { + "EventCode": "0x03A4", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access." + }, + { + "EventCode": "0x03A5", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR", + "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access." + }, + { + "EventCode": "0x03A6", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_L_MEM", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests." + }, + { + "EventCode": "0x03A7", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_MEM", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests." + }, + { + "EventCode": "0x03A8", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_L_L2", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests." + }, + { + "EventCode": "0x03A9", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L2", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests." + }, + { + "EventCode": "0x03AA", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L3", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests." + }, + { + "EventCode": "0x03AB", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L2", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests." + }, + { + "EventCode": "0x03AC", + "EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L3", + "BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests." + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD", + "BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json new file mode 100644 index 000000000000..a441b84729ab --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "LL_CACHE_RD", + "BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events." + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD", + "BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/memory.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/memory.json new file mode 100644 index 000000000000..4ef125e3a253 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/memory.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS", + "BriefDescription": "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LDST_SPEC events." + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + "BriefDescription": "This event counts architecturally executed memory-reading instructions, as defined by the LD_SPEC events." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pipeline.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pipeline.json new file mode 100644 index 000000000000..3cc3105f4a5e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pipeline.json @@ -0,0 +1,208 @@ +[ + { + "EventCode": "0x01A0", + "EventName": "EAGA_VAL", + "BriefDescription": "This event counts valid cycles of EAGA pipeline." + }, + { + "EventCode": "0x01A1", + "EventName": "EAGB_VAL", + "BriefDescription": "This event counts valid cycles of EAGB pipeline." + }, + { + "EventCode": "0x01A3", + "EventName": "PRX_VAL", + "BriefDescription": "This event counts valid cycles of PRX pipeline." + }, + { + "EventCode": "0x01A4", + "EventName": "EXA_VAL", + "BriefDescription": "This event counts valid cycles of EXA pipeline." + }, + { + "EventCode": "0x01A5", + "EventName": "EXB_VAL", + "BriefDescription": "This event counts valid cycles of EXB pipeline." + }, + { + "EventCode": "0x01A6", + "EventName": "EXC_VAL", + "BriefDescription": "This event counts valid cycles of EXC pipeline." + }, + { + "EventCode": "0x01A7", + "EventName": "EXD_VAL", + "BriefDescription": "This event counts valid cycles of EXD pipeline." + }, + { + "EventCode": "0x01A8", + "EventName": "FLA_VAL", + "BriefDescription": "This event counts valid cycles of FLA pipeline." + }, + { + "EventCode": "0x01A9", + "EventName": "FLB_VAL", + "BriefDescription": "This event counts valid cycles of FLB pipeline." + }, + { + "EventCode": "0x01AA", + "EventName": "STEA_VAL", + "BriefDescription": "This event counts valid cycles of STEA pipeline." + }, + { + "EventCode": "0x01AB", + "EventName": "STEB_VAL", + "BriefDescription": "This event counts valid cycles of STEB pipeline." + }, + { + "EventCode": "0x01AC", + "EventName": "STFL_VAL", + "BriefDescription": "This event counts valid cycles of STFL pipeline." + }, + { + "EventCode": "0x01AD", + "EventName": "STPX_VAL", + "BriefDescription": "This event counts valid cycles of STPX pipeline." + }, + { + "EventCode": "0x01B0", + "EventName": "FLA_VAL_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 32 when all bits are 1." + }, + { + "EventCode": "0x01B1", + "EventName": "FLB_VAL_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 32 when all bits are 1." + }, + { + "EventCode": "0x01B2", + "EventName": "FLA_VAL_FOR_PRD", + "BriefDescription": "This event counts valid cycles of FLA pipeline." + }, + { + "EventCode": "0x01B3", + "EventName": "FLB_VAL_FOR_PRD", + "BriefDescription": "This event counts valid cycles of FLB pipeline." + }, + { + "EventCode": "0x0240", + "EventName": "L1_PIPE0_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." + }, + { + "EventCode": "0x0241", + "EventName": "L1_PIPE1_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." + }, + { + "EventCode": "0x0242", + "EventName": "L1_PIPE2_VAL", + "BriefDescription": "This event counts valid cycles of L1D cache pipeline#2." + }, + { + "EventCode": "0x0250", + "EventName": "L1_PIPE0_COMP", + "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." + }, + { + "EventCode": "0x0251", + "EventName": "L1_PIPE1_COMP", + "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." + }, + { + "EventCode": "0x025A", + "EventName": "L1_PIPE_ABORT_STLD_INTLK", + "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." + }, + { + "EventCode": "0x026C", + "EventName": "L1I_PIPE_COMP", + "BriefDescription": "This event counts completed requests in L1I cache pipeline." + }, + { + "EventCode": "0x026D", + "EventName": "L1I_PIPE_VAL", + "BriefDescription": "This event counts valid cycles of L1I cache pipeline." + }, + { + "EventCode": "0x0278", + "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." + }, + { + "EventCode": "0x0279", + "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." + }, + { + "EventCode": "0x02A0", + "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", + "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." + }, + { + "EventCode": "0x02A1", + "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", + "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." + }, + { + "EventCode": "0x02B0", + "EventName": "L1_PIPE_COMP_GATHER_2FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." + }, + { + "EventCode": "0x02B1", + "EventName": "L1_PIPE_COMP_GATHER_1FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." + }, + { + "EventCode": "0x02B2", + "EventName": "L1_PIPE_COMP_GATHER_0FLOW", + "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." + }, + { + "EventCode": "0x02B3", + "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", + "BriefDescription": "This event counts the number of flows of the scatter instructions." + }, + { + "EventCode": "0x02B8", + "EventName": "L1_PIPE0_COMP_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 64 when all bits are 1." + }, + { + "EventCode": "0x02B9", + "EventName": "L1_PIPE1_COMP_PRD_CNT", + "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 64 when all bits are 1." + }, + { + "EventCode": "0x0330", + "EventName": "L2_PIPE_VAL", + "BriefDescription": "This event counts valid cycles of L2 cache pipeline." + }, + { + "EventCode": "0x0350", + "EventName": "L2_PIPE_COMP_ALL", + "BriefDescription": "This event counts completed requests in L2 cache pipeline." + }, + { + "EventCode": "0x0370", + "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", + "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." + }, + { + "ArchStdEvent": "STALL_FRONTEND_TLB", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the instruction TLB." + }, + { + "ArchStdEvent": "STALL_BACKEND_TLB", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in the data TLB." + }, + { + "ArchStdEvent": "STALL_BACKEND_ST", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is stalled waiting for a store." + }, + { + "ArchStdEvent": "STALL_BACKEND_ILOCK", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but at least one is not ready to be sent to the backend because of an input dependency." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pmu.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pmu.json new file mode 100644 index 000000000000..65bd6cdd0dd5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/pmu.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "PMU_OVFS", + "BriefDescription": "This event counts the event generated each time one of the condition occurs described in Arm Architecture Reference Manual for A-profile architecture. This event is only for output to the trace unit." + }, + { + "ArchStdEvent": "PMU_HOVFS", + "BriefDescription": "This event counts the event generated each time an event is counted by an event counter <n> and all of the condition occur described in Arm Architecture Reference Manual for A-profile architecture. This event is only for output to the trace unit." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/retired.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/retired.json new file mode 100644 index 000000000000..de56aafec2dc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/retired.json @@ -0,0 +1,30 @@ +[ + { + "ArchStdEvent": "SW_INCR", + "BriefDescription": "This event counts on writes to the PMSWINC register." + }, + { + "ArchStdEvent": "INST_RETIRED", + "BriefDescription": "This event counts every architecturally executed instruction." + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED", + "BriefDescription": "This event counts every write to CONTEXTIDR." + }, + { + "ArchStdEvent": "BR_RETIRED", + "BriefDescription": "This event counts architecturally executed branch instruction." + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED", + "BriefDescription": "This event counts architecturally executed branch instruction which was mispredicted." + }, + { + "ArchStdEvent": "OP_RETIRED", + "BriefDescription": "This event counts every architecturally executed micro-operation." + }, + { + "ArchStdEvent": "UOP_RETIRED", + "BriefDescription": "This event counts micro-operation that would be executed in a Simple sequential execution of the program." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/spec_operation.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/spec_operation.json new file mode 100644 index 000000000000..4841b43e2871 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/spec_operation.json @@ -0,0 +1,171 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED", + "BriefDescription": "This event counts each correction to the predicted program flow that occurs because of a misprediction from, or no prediction from, the branch prediction resources and that relates to instructions that the branch prediction resources are capable of predicting." + }, + { + "ArchStdEvent": "BR_PRED", + "BriefDescription": "This event counts every branch or other change in the program flow that the branch prediction resources are capable of predicting." + }, + { + "ArchStdEvent": "INST_SPEC", + "BriefDescription": "This event counts every architecturally executed instruction." + }, + { + "ArchStdEvent": "OP_SPEC", + "BriefDescription": "This event counts every speculatively executed micro-operation." + }, + { + "ArchStdEvent": "LDREX_SPEC", + "BriefDescription": "This event counts architecturally executed load-exclusive instructions." + }, + { + "ArchStdEvent": "STREX_SPEC", + "BriefDescription": "This event counts architecturally executed store-exclusive instructions." + }, + { + "ArchStdEvent": "LD_SPEC", + "BriefDescription": "This event counts architecturally executed memory-reading instructions, as defined by the LD_RETIRED event." + }, + { + "ArchStdEvent": "ST_SPEC", + "BriefDescription": "This event counts architecturally executed memory-writing instructions, as defined by the ST_RETIRED event. This event counts DCZVA as a store operation." + }, + { + "ArchStdEvent": "LDST_SPEC", + "BriefDescription": "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LD_RETIRED and ST_RETIRED events." + }, + { + "ArchStdEvent": "DP_SPEC", + "BriefDescription": "This event counts architecturally executed integer data-processing instructions. See DP_SPEC of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "ASE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD data-processing instructions." + }, + { + "ArchStdEvent": "VFP_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point data-processing instructions." + }, + { + "ArchStdEvent": "PC_WRITE_SPEC", + "BriefDescription": "This event counts only software changes of the PC that defined by the instruction architecturally executed, condition code check pass, software change of the PC event." + }, + { + "ArchStdEvent": "CRYPTO_SPEC", + "BriefDescription": "This event counts architecturally executed cryptographic instructions, except PMULL and VMULL." + }, + { + "ArchStdEvent": "BR_IMMED_SPEC", + "BriefDescription": "This event counts architecturally executed immediate branch instructions." + }, + { + "ArchStdEvent": "BR_RETURN_SPEC", + "BriefDescription": "This event counts architecturally executed procedure return operations that defined by the BR_RETURN_RETIRED event." + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC", + "BriefDescription": "This event counts architecturally executed indirect branch instructions that includes software change of the PC other than exception-generating instructions and immediate branch instructions." + }, + { + "ArchStdEvent": "ISB_SPEC", + "BriefDescription": "This event counts architecturally executed Instruction Synchronization Barrier instructions." + }, + { + "ArchStdEvent": "DSB_SPEC", + "BriefDescription": "This event counts architecturally executed Data Synchronization Barrier instructions." + }, + { + "ArchStdEvent": "DMB_SPEC", + "BriefDescription": "This event counts architecturally executed Data Memory Barrier instructions, excluding the implied barrier operations of load/store operations with release consistency semantics." + }, + { + "ArchStdEvent": "CSDB_SPEC", + "BriefDescription": "This event counts speculatively executed control speculation barrier instructions." + }, + { + "EventCode": "0x0108", + "EventName": "PRD_SPEC", + "BriefDescription": "This event counts architecturally executed operations that using predicate register." + }, + { + "EventCode": "0x0109", + "EventName": "IEL_SPEC", + "BriefDescription": "This event counts architecturally executed inter-element manipulation operations." + }, + { + "EventCode": "0x010A", + "EventName": "IREG_SPEC", + "BriefDescription": "This event counts architecturally executed inter-register manipulation operations." + }, + { + "EventCode": "0x011A", + "EventName": "BC_LD_SPEC", + "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations." + }, + { + "EventCode": "0x011B", + "EventName": "DCZVA_SPEC", + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the DC ZVA instruction." + }, + { + "EventCode": "0x0121", + "EventName": "EFFECTIVE_INST_SPEC", + "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction." + }, + { + "EventCode": "0x0123", + "EventName": "PRE_INDEX_SPEC", + "BriefDescription": "This event counts architecturally executed operations that uses pre-index as its addressing mode." + }, + { + "EventCode": "0x0124", + "EventName": "POST_INDEX_SPEC", + "BriefDescription": "This event counts architecturally executed operations that uses post-index as its addressing mode." + }, + { + "EventCode": "0x0139", + "EventName": "UOP_SPLIT", + "BriefDescription": "This event counts the occurrence count of the micro-operation split." + }, + { + "ArchStdEvent": "ASE_INST_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD operations." + }, + { + "ArchStdEvent": "INT_SPEC", + "BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Integer instructions section of ARMv9 Reference Manual." + }, + { + "ArchStdEvent": "INT_DIV_SPEC", + "BriefDescription": "This event counts architecturally executed integer divide operation." + }, + { + "ArchStdEvent": "INT_DIV64_SPEC", + "BriefDescription": "This event counts architecturally executed 64-bit integer divide operation." + }, + { + "ArchStdEvent": "INT_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed integer multiply operation." + }, + { + "ArchStdEvent": "INT_MUL64_SPEC", + "BriefDescription": "This event counts architecturally executed integer 64-bit x 64-bit multiply operation." + }, + { + "ArchStdEvent": "INT_MULH64_SPEC", + "BriefDescription": "This event counts architecturally executed integer 64-bit x 64-bit multiply returning high part operation." + }, + { + "ArchStdEvent": "NONFP_SPEC", + "BriefDescription": "This event counts architecturally executed non-floating-point operations." + }, + { + "ArchStdEvent": "INT_SCALE_OPS_SPEC", + "BriefDescription": "This event counts each integer ALU operation counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction." + }, + { + "ArchStdEvent": "INT_FIXED_OPS_SPEC", + "BriefDescription": "This event counts each integer ALU operation counted by INT_SPEC that is not counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json new file mode 100644 index 000000000000..5fb81e2a0a07 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json @@ -0,0 +1,94 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND", + "BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because there are no operations available to issue for this PE from the frontend." + }, + { + "ArchStdEvent": "STALL_BACKEND", + "BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operations." + }, + { + "ArchStdEvent": "STALL", + "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit." + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND", + "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the backend." + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND", + "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the frontend." + }, + { + "ArchStdEvent": "STALL_SLOT", + "BriefDescription": "This event counts every cycle that no instruction or operation Slot was dispatched from decode unit." + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM", + "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to memory stall." + }, + { + "ArchStdEvent": "STALL_FRONTEND_MEMBOUND", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when no instructions are delivered from the memory system." + }, + { + "ArchStdEvent": "STALL_FRONTEND_L1I", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the first level of instruction cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_L2I", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the second level of instruction cache." + }, + { + "ArchStdEvent": "STALL_FRONTEND_MEM", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the last level of instruction cache within the PE clock domain or a non-cacheable instruction fetch in progress." + }, + { + "ArchStdEvent": "STALL_FRONTEND_CPUBOUND", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when the frontend is stalled on a frontend processor resource, not including memory." + }, + { + "ArchStdEvent": "STALL_FRONTEND_FLOW", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is stalled on unavailability of prediction flow resources." + }, + { + "ArchStdEvent": "STALL_FRONTEND_FLUSH", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is recovering from a pipeline flush." + }, + { + "ArchStdEvent": "STALL_FRONTEND_RENAME", + "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available." + }, + { + "ArchStdEvent": "STALL_BACKEND_MEMBOUND", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is waiting for a memory access to complete." + }, + { + "ArchStdEvent": "STALL_BACKEND_L1D", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L1D cache." + }, + { + "ArchStdEvent": "STALL_BACKEND_L2D", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2D cache." + }, + { + "ArchStdEvent": "STALL_BACKEND_CPUBOUND", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is stalled on a processor resource, not including memory." + }, + { + "ArchStdEvent": "STALL_BACKEND_BUSY", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but the backend is not able to accept an operation because an execution unit is busy." + }, + { + "ArchStdEvent": "STALL_BACKEND_RENAME", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available." + }, + { + "ArchStdEvent": "STALL_BACKEND_ATOMIC", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing an Atomic operation." + }, + { + "ArchStdEvent": "STALL_BACKEND_MEMCPYSET", + "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing a Memory Copy or Set instruction." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/sve.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/sve.json new file mode 100644 index 000000000000..e66b5af00f90 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/sve.json @@ -0,0 +1,254 @@ +[ + { + "ArchStdEvent": "SIMD_INST_RETIRED", + "BriefDescription": "This event counts architecturally executed SIMD instructions, excluding the Advanced SIMD scalar instructions and the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual." + }, + { + "ArchStdEvent": "SVE_INST_RETIRED", + "BriefDescription": "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual." + }, + { + "ArchStdEvent": "SVE_INST_SPEC", + "BriefDescription": "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual." + }, + { + "ArchStdEvent": "ASE_SVE_INST_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE operations." + }, + { + "ArchStdEvent": "UOP_SPEC", + "BriefDescription": "This event counts all architecturally executed micro-operations." + }, + { + "ArchStdEvent": "SVE_MATH_SPEC", + "BriefDescription": "This event counts architecturally executed math function operations due to the SVE FTSMUL, FTMAD, FTSSEL, and FEXPA instructions." + }, + { + "ArchStdEvent": "FP_SPEC", + "BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Floating-point instructions section of ARMv9 Reference Manual." + }, + { + "ArchStdEvent": "FP_FMA_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations." + }, + { + "ArchStdEvent": "FP_RECPE_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point reciprocal estimate operations due to the Advanced SIMD scalar, Advanced SIMD vector, and SVE FRECPE and FRSQRTE instructions." + }, + { + "ArchStdEvent": "FP_CVT_SPEC", + "BriefDescription": "This event counts architecturally executed floating-point convert operations due to the scalar, Advanced SIMD, and SVE floating-point conversion instructions listed in Floating-point conversions section of ARMv9 Reference Manual." + }, + { + "ArchStdEvent": "ASE_INT_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD integer operations." + }, + { + "ArchStdEvent": "SVE_INT_SPEC", + "BriefDescription": "This event counts architecturally executed SVE integer operations." + }, + { + "ArchStdEvent": "ASE_SVE_INT_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer operations." + }, + { + "ArchStdEvent": "SVE_INT_DIV_SPEC", + "BriefDescription": "This event counts architecturally executed SVE integer divide operation." + }, + { + "ArchStdEvent": "SVE_INT_DIV64_SPEC", + "BriefDescription": "This event counts architecturally executed SVE 64-bit integer divide operation." + }, + { + "ArchStdEvent": "ASE_INT_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD integer multiply operation." + }, + { + "ArchStdEvent": "SVE_INT_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed SVE integer multiply operation." + }, + { + "ArchStdEvent": "ASE_SVE_INT_MUL_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer multiply operations." + }, + { + "ArchStdEvent": "SVE_INT_MUL64_SPEC", + "BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply operation." + }, + { + "ArchStdEvent": "SVE_INT_MULH64_SPEC", + "BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operations." + }, + { + "ArchStdEvent": "ASE_NONFP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD non-floating-point operations." + }, + { + "ArchStdEvent": "SVE_NONFP_SPEC", + "BriefDescription": "This event counts architecturally executed SVE non-floating-point operations." + }, + { + "ArchStdEvent": "ASE_SVE_NONFP_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE non-floating-point operations." + }, + { + "ArchStdEvent": "ASE_INT_VREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD integer reduction operation." + }, + { + "ArchStdEvent": "SVE_INT_VREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed SVE integer reduction operation." + }, + { + "ArchStdEvent": "ASE_SVE_INT_VREDUCE_SPEC", + "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer reduction operations." + }, + { + "ArchStdEvent": "SVE_PERM_SPEC", + "BriefDescription": "This event counts architecturally executed vector or predicate permute operation." + }, + { + "ArchStdEvent": "SVE_XPIPE_Z2R_SPEC", + "BriefDescription": "This event counts architecturally executed vector to general-purpose scalar cross-pipeline transfer operation." + }, + { + "ArchStdEvent": "SVE_XPIPE_R2Z_SPEC", + "BriefDescription": "This event counts architecturally executed general-purpose scalar to vector cross-pipeline transfer operation." + }, + { + "ArchStdEvent": "SVE_PGEN_SPEC", + "BriefDescription": "This event counts architecturally executed predicate-generating operation." + }, + { + "ArchStdEvent": "SVE_PGEN_FLG_SPEC", + "BriefDescription": "This event counts architecturally executed predicate-generating operation that sets condition flags." + }, + { + "ArchStdEvent": "SVE_PPERM_SPEC", + "BriefDescription": "This event counts architecturally executed predicate permute operation." + }, + { + "ArchStdEvent": "SVE_PRED_SPEC", + "BriefDescription": "This event counts architecturally executed SIMD data-processing and load/store operations due to SVE instructions with a Governing predicate operand that determines the Active elements." + }, + { + "ArchStdEvent": "SVE_MOVPRFX_SPEC", + "BriefDescription": "This event counts architecturally executed operations due to MOVPRFX instructions, whether or not they were fused with the prefixed instruction." + }, + { + "ArchStdEvent": "SVE_MOVPRFX_Z_SPEC", + "BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses zeroing predication." + }, + { + "ArchStdEvent": "SVE_MOVPRFX_M_SPEC", + "BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses merging predication." + }, + { + "ArchStdEvent": "SVE_MOVPRFX_U_SPEC", + "BriefDescription": "This event counts architecturally executed operations due to MOVPRFX instructions that were not fused with the prefixed instruction." + }, + { + "ArchStdEvent": "ASE_SVE_LD_SPEC", + "BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions." + }, + { + "ArchStdEvent": "ASE_SVE_ST_SPEC", + "BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions." + }, + { + "ArchStdEvent": "PRF_SPEC", + "BriefDescription": "This event counts architecturally executed prefetch operations due to scalar PRFM, PRFUM and SVE PRF instructions." + }, + { + "ArchStdEvent": "BASE_LD_REG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that read from memory due to an instruction that loads a general-purpose register." + }, + { + "ArchStdEvent": "BASE_ST_REG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that write to memory due to an instruction that stores a general-purpose register, excluding the DC ZVA instruction." + }, + { + "ArchStdEvent": "SVE_LDR_REG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that read from memory due to an SVE LDR instruction." + }, + { + "ArchStdEvent": "SVE_STR_REG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that write to memory due to an SVE STR instruction." + }, + { + "ArchStdEvent": "SVE_LDR_PREG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that read from memory due to an SVE LDR (predicate) instruction." + }, + { + "ArchStdEvent": "SVE_STR_PREG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that write to memory due to an SVE STR (predicate) instruction." + }, + { + "ArchStdEvent": "SVE_PRF_CONTIG_SPEC", + "BriefDescription": "This event counts architecturally executed operations that prefetch memory due to an SVE predicated single contiguous element prefetch instruction." + }, + { + "ArchStdEvent": "SVE_LDNT_CONTIG_SPEC", + "BriefDescription": "This event counts architecturally executed operation that reads from memory with a non-temporal hint due to an SVE non-temporal contiguous element load instruction." + }, + { + "ArchStdEvent": "SVE_STNT_CONTIG_SPEC", + "BriefDescription": "This event counts architecturally executed operation that writes to memory with a non-temporal hint due to an SVE non-temporal contiguous element store instruction." + }, + { + "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC", + "BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions." + }, + { + "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC", + "BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions." + }, + { + "ArchStdEvent": "SVE_LD_GATHER_SPEC", + "BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE non-contiguous gather-load instructions." + }, + { + "ArchStdEvent": "SVE_ST_SCATTER_SPEC", + "BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE non-contiguous scatter-store instructions." + }, + { + "ArchStdEvent": "SVE_PRF_GATHER_SPEC", + "BriefDescription": "This event counts architecturally executed operations that prefetch memory due to SVE non-contiguous gather-prefetch instructions." + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC", + "BriefDescription": "This event counts architecturally executed memory read operations due to SVE First-fault and Non-fault load instructions." + }, + { + "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed SVE half-precision arithmetic operations. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC." + }, + { + "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operations. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC." + }, + { + "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed SVE single-precision arithmetic operations. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC." + }, + { + "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operations. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC." + }, + { + "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed SVE double-precision arithmetic operations. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC." + }, + { + "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC", + "BriefDescription": "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operations. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC." + }, + { + "ArchStdEvent": "ASE_SVE_INT_DOT_SPEC", + "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer dot-product operation." + }, + { + "ArchStdEvent": "ASE_SVE_INT_MMLA_SPEC", + "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer matrix multiply operation." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/tlb.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/tlb.json new file mode 100644 index 000000000000..edc7cb8696c8 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/tlb.json @@ -0,0 +1,362 @@ +[ + { + "ArchStdEvent": "L1I_TLB_REFILL", + "BriefDescription": "This event counts operations that cause a TLB refill of the L1I TLB. See L1I_TLB_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL", + "BriefDescription": "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_TLB_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1D_TLB", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_TLB of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L1I_TLB", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_TLB of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL", + "BriefDescription": "This event counts operations that cause a TLB refill of the L2D TLB. See L2D_TLB_REFILL of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "L2D_TLB", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_TLB of ARMv9 Reference Manual for more information." + }, + { + "ArchStdEvent": "DTLB_WALK", + "BriefDescription": "This event counts data TLB access with at least one translation table walk." + }, + { + "ArchStdEvent": "ITLB_WALK", + "BriefDescription": "This event counts instruction TLB access with at least one translation table walk." + }, + { + "EventCode": "0x0C00", + "EventName": "L1I_TLB_4K", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page." + }, + { + "EventCode": "0x0C01", + "EventName": "L1I_TLB_64K", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page." + }, + { + "EventCode": "0x0C02", + "EventName": "L1I_TLB_2M", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page." + }, + { + "EventCode": "0x0C03", + "EventName": "L1I_TLB_32M", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page." + }, + { + "EventCode": "0x0C04", + "EventName": "L1I_TLB_512M", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 512MB page." + }, + { + "EventCode": "0x0C05", + "EventName": "L1I_TLB_1G", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 1GB page." + }, + { + "EventCode": "0x0C06", + "EventName": "L1I_TLB_16G", + "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 16GB page." + }, + { + "EventCode": "0x0C08", + "EventName": "L1D_TLB_4K", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 4KB page." + }, + { + "EventCode": "0x0C09", + "EventName": "L1D_TLB_64K", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 64KB page." + }, + { + "EventCode": "0x0C0A", + "EventName": "L1D_TLB_2M", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 2MB page." + }, + { + "EventCode": "0x0C0B", + "EventName": "L1D_TLB_32M", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 32MB page." + }, + { + "EventCode": "0x0C0C", + "EventName": "L1D_TLB_512M", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 512MB page." + }, + { + "EventCode": "0x0C0D", + "EventName": "L1D_TLB_1G", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 1GB page." + }, + { + "EventCode": "0x0C0E", + "EventName": "L1D_TLB_16G", + "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 16GB page." + }, + { + "EventCode": "0x0C10", + "EventName": "L1I_TLB_REFILL_4K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 4KB page." + }, + { + "EventCode": "0x0C11", + "EventName": "L1I_TLB_REFILL_64K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 64KB page." + }, + { + "EventCode": "0x0C12", + "EventName": "L1I_TLB_REFILL_2M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 2MB page." + }, + { + "EventCode": "0x0C13", + "EventName": "L1I_TLB_REFILL_32M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 32MB page." + }, + { + "EventCode": "0x0C14", + "EventName": "L1I_TLB_REFILL_512M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 512MB page." + }, + { + "EventCode": "0x0C15", + "EventName": "L1I_TLB_REFILL_1G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 1GB page." + }, + { + "EventCode": "0x0C16", + "EventName": "L1I_TLB_REFILL_16G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 16GB page." + }, + { + "EventCode": "0x0C18", + "EventName": "L1D_TLB_REFILL_4K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 4KB page." + }, + { + "EventCode": "0x0C19", + "EventName": "L1D_TLB_REFILL_64K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 64KB page." + }, + { + "EventCode": "0x0C1A", + "EventName": "L1D_TLB_REFILL_2M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 2MB page." + }, + { + "EventCode": "0x0C1B", + "EventName": "L1D_TLB_REFILL_32M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 32MB page." + }, + { + "EventCode": "0x0C1C", + "EventName": "L1D_TLB_REFILL_512M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 512MB page." + }, + { + "EventCode": "0x0C1D", + "EventName": "L1D_TLB_REFILL_1G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 1GB page." + }, + { + "EventCode": "0x0C1E", + "EventName": "L1D_TLB_REFILL_16G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 16GB page." + }, + { + "EventCode": "0x0C20", + "EventName": "L2I_TLB_4K", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 4KB page." + }, + { + "EventCode": "0x0C21", + "EventName": "L2I_TLB_64K", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 64KB page." + }, + { + "EventCode": "0x0C22", + "EventName": "L2I_TLB_2M", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 2MB page." + }, + { + "EventCode": "0x0C23", + "EventName": "L2I_TLB_32M", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 32MB page." + }, + { + "EventCode": "0x0C24", + "EventName": "L2I_TLB_512M", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 512MB page." + }, + { + "EventCode": "0x0C25", + "EventName": "L2I_TLB_1G", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 1GB page." + }, + { + "EventCode": "0x0C26", + "EventName": "L2I_TLB_16G", + "BriefDescription": "This event counts operations that cause a TLB access to the L2I in 16GB page." + }, + { + "EventCode": "0x0C28", + "EventName": "L2D_TLB_4K", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 4KB page." + }, + { + "EventCode": "0x0C29", + "EventName": "L2D_TLB_64K", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 64KB page." + }, + { + "EventCode": "0x0C2A", + "EventName": "L2D_TLB_2M", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 2MB page." + }, + { + "EventCode": "0x0C2B", + "EventName": "L2D_TLB_32M", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 32MB page." + }, + { + "EventCode": "0x0C2C", + "EventName": "L2D_TLB_512M", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 512MB page." + }, + { + "EventCode": "0x0C2D", + "EventName": "L2D_TLB_1G", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 1GB page." + }, + { + "EventCode": "0x0C2E", + "EventName": "L2D_TLB_16G", + "BriefDescription": "This event counts operations that cause a TLB access to the L2D in 16GB page." + }, + { + "EventCode": "0x0C30", + "EventName": "L2I_TLB_REFILL_4K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2Iin 4KB page." + }, + { + "EventCode": "0x0C31", + "EventName": "L2I_TLB_REFILL_64K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 64KB page." + }, + { + "EventCode": "0x0C32", + "EventName": "L2I_TLB_REFILL_2M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 2MB page." + }, + { + "EventCode": "0x0C33", + "EventName": "L2I_TLB_REFILL_32M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 32MB page." + }, + { + "EventCode": "0x0C34", + "EventName": "L2I_TLB_REFILL_512M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 512MB page." + }, + { + "EventCode": "0x0C35", + "EventName": "L2I_TLB_REFILL_1G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 1GB page." + }, + { + "EventCode": "0x0C36", + "EventName": "L2I_TLB_REFILL_16G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 16GB page." + }, + { + "EventCode": "0x0C38", + "EventName": "L2D_TLB_REFILL_4K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 4KB page." + }, + { + "EventCode": "0x0C39", + "EventName": "L2D_TLB_REFILL_64K", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 64KB page." + }, + { + "EventCode": "0x0C3A", + "EventName": "L2D_TLB_REFILL_2M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 2MB page." + }, + { + "EventCode": "0x0C3B", + "EventName": "L2D_TLB_REFILL_32M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 32MB page." + }, + { + "EventCode": "0x0C3C", + "EventName": "L2D_TLB_REFILL_512M", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 512MB page." + }, + { + "EventCode": "0x0C3D", + "EventName": "L2D_TLB_REFILL_1G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 1GB page." + }, + { + "EventCode": "0x0C3E", + "EventName": "L2D_TLB_REFILL_16G", + "BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 16GB page." + }, + { + "ArchStdEvent": "DTLB_WALK_PERCYC", + "BriefDescription": "This event counts the number of DTLB_WALK events in progress on each Processor cycle." + }, + { + "ArchStdEvent": "ITLB_WALK_PERCYC", + "BriefDescription": "This event counts the number of ITLB_WALK events in progress on each Processor cycle." + }, + { + "ArchStdEvent": "DTLB_STEP", + "BriefDescription": "This event counts translation table walk access made by a refill of the data TLB." + }, + { + "ArchStdEvent": "ITLB_STEP", + "BriefDescription": "This event counts translation table walk access made by a refill of the instruction TLB." + }, + { + "ArchStdEvent": "DTLB_WALK_LARGE", + "BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a large page size." + }, + { + "ArchStdEvent": "ITLB_WALK_LARGE", + "BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a large page size." + }, + { + "ArchStdEvent": "DTLB_WALK_SMALL", + "BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a small page size." + }, + { + "ArchStdEvent": "ITLB_WALK_SMALL", + "BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a small page size." + }, + { + "ArchStdEvent": "DTLB_WALK_BLOCK", + "BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a Block." + }, + { + "ArchStdEvent": "ITLB_WALK_BLOCK", + "BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a Block." + }, + { + "ArchStdEvent": "DTLB_WALK_PAGE", + "BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a Page." + }, + { + "ArchStdEvent": "ITLB_WALK_PAGE", + "BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a Page." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/trace.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/trace.json new file mode 100644 index 000000000000..0c6e5054c9b5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/trace.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "TRB_WRAP", + "BriefDescription": "This event counts the event generated each time the current write pointer is wrapped to the base pointer." + }, + { + "ArchStdEvent": "TRB_TRIG", + "BriefDescription": "This event counts the event generated when a Trace Buffer Extension Trigger Event occurs." + }, + { + "ArchStdEvent": "TRCEXTOUT0", + "BriefDescription": "This event counts the event generated each time an event is signaled by the trace unit external event 0." + }, + { + "ArchStdEvent": "CTI_TRIGOUT4", + "BriefDescription": "This event counts the event generated each time an event is signaled on CTI output trigger 4." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json index 6463531b9941..b6a0d2de8534 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json @@ -3,235 +3,235 @@ "MetricExpr": "FETCH_BUBBLE / (4 * CPU_CYCLES)", "PublicDescription": "Frontend bound L1 topdown metric", "BriefDescription": "Frontend bound L1 topdown metric", - "DefaultMetricgroupName": "TopDownL1", - "MetricGroup": "Default;TopDownL1", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", "MetricName": "frontend_bound" }, { "MetricExpr": "(INST_SPEC - INST_RETIRED) / (4 * CPU_CYCLES)", "PublicDescription": "Bad Speculation L1 topdown metric", "BriefDescription": "Bad Speculation L1 topdown metric", - "DefaultMetricgroupName": "TopDownL1", - "MetricGroup": "Default;TopDownL1", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", "MetricName": "bad_speculation" }, { "MetricExpr": "INST_RETIRED / (CPU_CYCLES * 4)", "PublicDescription": "Retiring L1 topdown metric", "BriefDescription": "Retiring L1 topdown metric", - "DefaultMetricgroupName": "TopDownL1", - "MetricGroup": "Default;TopDownL1", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", "MetricName": "retiring" }, { "MetricExpr": "1 - (frontend_bound + bad_speculation + retiring)", "PublicDescription": "Backend Bound L1 topdown metric", "BriefDescription": "Backend Bound L1 topdown metric", - "DefaultMetricgroupName": "TopDownL1", - "MetricGroup": "Default;TopDownL1", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", "MetricName": "backend_bound" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x201d@ / CPU_CYCLES", "PublicDescription": "Fetch latency bound L2 topdown metric", "BriefDescription": "Fetch latency bound L2 topdown metric", - "MetricGroup": "TopDownL2", + "MetricGroup": "TopdownL2", "MetricName": "fetch_latency_bound" }, { "MetricExpr": "frontend_bound - fetch_latency_bound", "PublicDescription": "Fetch bandwidth bound L2 topdown metric", "BriefDescription": "Fetch bandwidth bound L2 topdown metric", - "MetricGroup": "TopDownL2", + "MetricGroup": "TopdownL2", "MetricName": "fetch_bandwidth_bound" }, { "MetricExpr": "(bad_speculation * BR_MIS_PRED) / (BR_MIS_PRED + armv8_pmuv3_0@event\\=0x2013@)", "PublicDescription": "Branch mispredicts L2 topdown metric", "BriefDescription": "Branch mispredicts L2 topdown metric", - "MetricGroup": "TopDownL2", + "MetricGroup": "TopdownL2", "MetricName": "branch_mispredicts" }, { "MetricExpr": "bad_speculation - branch_mispredicts", "PublicDescription": "Machine clears L2 topdown metric", "BriefDescription": "Machine clears L2 topdown metric", - "MetricGroup": "TopDownL2", + "MetricGroup": "TopdownL2", "MetricName": "machine_clears" }, { "MetricExpr": "(EXE_STALL_CYCLE - (MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@)) / CPU_CYCLES", "PublicDescription": "Core bound L2 topdown metric", "BriefDescription": "Core bound L2 topdown metric", - "MetricGroup": "TopDownL2", + "MetricGroup": "TopdownL2", "MetricName": "core_bound" }, { "MetricExpr": "(MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@) / CPU_CYCLES", "PublicDescription": "Memory bound L2 topdown metric", "BriefDescription": "Memory bound L2 topdown metric", - "MetricGroup": "TopDownL2", + "MetricGroup": "TopdownL2", "MetricName": "memory_bound" }, { "MetricExpr": "(((L2I_TLB - L2I_TLB_REFILL) * 15) + (L2I_TLB_REFILL * 100)) / CPU_CYCLES", "PublicDescription": "Idle by itlb miss L3 topdown metric", "BriefDescription": "Idle by itlb miss L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "idle_by_itlb_miss" }, { "MetricExpr": "(((L2I_CACHE - L2I_CACHE_REFILL) * 15) + (L2I_CACHE_REFILL * 100)) / CPU_CYCLES", "PublicDescription": "Idle by icache miss L3 topdown metric", "BriefDescription": "Idle by icache miss L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "idle_by_icache_miss" }, { "MetricExpr": "(BR_MIS_PRED * 5) / CPU_CYCLES", "PublicDescription": "BP misp flush L3 topdown metric", "BriefDescription": "BP misp flush L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "bp_misp_flush" }, { "MetricExpr": "(armv8_pmuv3_0@event\\=0x2013@ * 5) / CPU_CYCLES", "PublicDescription": "OOO flush L3 topdown metric", "BriefDescription": "OOO flush L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "ooo_flush" }, { "MetricExpr": "(armv8_pmuv3_0@event\\=0x1001@ * 5) / CPU_CYCLES", "PublicDescription": "Static predictor flush L3 topdown metric", "BriefDescription": "Static predictor flush L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "sp_flush" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x1010@ / BR_MIS_PRED", "PublicDescription": "Indirect branch L3 topdown metric", "BriefDescription": "Indirect branch L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "indirect_branch" }, { "MetricExpr": "(armv8_pmuv3_0@event\\=0x1013@ + armv8_pmuv3_0@event\\=0x1016@) / BR_MIS_PRED", "PublicDescription": "Push branch L3 topdown metric", "BriefDescription": "Push branch L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "push_branch" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x100d@ / BR_MIS_PRED", "PublicDescription": "Pop branch L3 topdown metric", "BriefDescription": "Pop branch L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "pop_branch" }, { "MetricExpr": "(BR_MIS_PRED - armv8_pmuv3_0@event\\=0x1010@ - armv8_pmuv3_0@event\\=0x1013@ - armv8_pmuv3_0@event\\=0x1016@ - armv8_pmuv3_0@event\\=0x100d@) / BR_MIS_PRED", "PublicDescription": "Other branch L3 topdown metric", "BriefDescription": "Other branch L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "other_branch" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x2012@ / armv8_pmuv3_0@event\\=0x2013@", "PublicDescription": "Nuke flush L3 topdown metric", "BriefDescription": "Nuke flush L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "nuke_flush" }, { "MetricExpr": "1 - nuke_flush", "PublicDescription": "Other flush L3 topdown metric", "BriefDescription": "Other flush L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "other_flush" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x2010@ / CPU_CYCLES", "PublicDescription": "Sync stall L3 topdown metric", "BriefDescription": "Sync stall L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "sync_stall" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x2004@ / CPU_CYCLES", "PublicDescription": "Rob stall L3 topdown metric", "BriefDescription": "Rob stall L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "rob_stall" }, { "MetricExpr": "(armv8_pmuv3_0@event\\=0x2006@ + armv8_pmuv3_0@event\\=0x2007@ + armv8_pmuv3_0@event\\=0x2008@) / CPU_CYCLES", "PublicDescription": "Ptag stall L3 topdown metric", "BriefDescription": "Ptag stall L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "ptag_stall" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x201e@ / CPU_CYCLES", "PublicDescription": "SaveOpQ stall L3 topdown metric", "BriefDescription": "SaveOpQ stall L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "saveopq_stall" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x2005@ / CPU_CYCLES", "PublicDescription": "PC buffer stall L3 topdown metric", "BriefDescription": "PC buffer stall L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "pc_buffer_stall" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x7002@ / CPU_CYCLES", "PublicDescription": "Divider L3 topdown metric", "BriefDescription": "Divider L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "divider" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x7003@ / CPU_CYCLES", "PublicDescription": "FSU stall L3 topdown metric", "BriefDescription": "FSU stall L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "fsu_stall" }, { "MetricExpr": "core_bound - divider - fsu_stall", "PublicDescription": "EXE ports util L3 topdown metric", "BriefDescription": "EXE ports util L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "exe_ports_util" }, { "MetricExpr": "(MEM_STALL_ANYLOAD - MEM_STALL_L1MISS) / CPU_CYCLES", "PublicDescription": "L1 bound L3 topdown metric", "BriefDescription": "L1 bound L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "l1_bound" }, { "MetricExpr": "(MEM_STALL_L1MISS - MEM_STALL_L2MISS) / CPU_CYCLES", "PublicDescription": "L2 bound L3 topdown metric", "BriefDescription": "L2 bound L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "l2_bound" }, { "MetricExpr": "MEM_STALL_L2MISS / CPU_CYCLES", "PublicDescription": "Mem bound L3 topdown metric", "BriefDescription": "Mem bound L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "mem_bound" }, { "MetricExpr": "armv8_pmuv3_0@event\\=0x7005@ / CPU_CYCLES", "PublicDescription": "Store bound L3 topdown metric", "BriefDescription": "Store bound L3 topdown metric", - "MetricGroup": "TopDownL3", + "MetricGroup": "TopdownL3", "MetricName": "store_bound" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json index 2b3cb55df288..014454d78293 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json @@ -3,56 +3,48 @@ "ConfigCode": "0x00", "EventName": "flux_wr", "BriefDescription": "DDRC total write operations", - "PublicDescription": "DDRC total write operations", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x01", "EventName": "flux_rd", "BriefDescription": "DDRC total read operations", - "PublicDescription": "DDRC total read operations", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x02", "EventName": "flux_wcmd", "BriefDescription": "DDRC write commands", - "PublicDescription": "DDRC write commands", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x03", "EventName": "flux_rcmd", "BriefDescription": "DDRC read commands", - "PublicDescription": "DDRC read commands", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x04", "EventName": "pre_cmd", "BriefDescription": "DDRC precharge commands", - "PublicDescription": "DDRC precharge commands", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x05", "EventName": "act_cmd", "BriefDescription": "DDRC active commands", - "PublicDescription": "DDRC active commands", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x06", "EventName": "rnk_chg", "BriefDescription": "DDRC rank commands", - "PublicDescription": "DDRC rank commands", "Unit": "hisi_sccl,ddrc" }, { "ConfigCode": "0x07", "EventName": "rw_chg", "BriefDescription": "DDRC read and write changes", - "PublicDescription": "DDRC read and write changes", "Unit": "hisi_sccl,ddrc" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json index 9a7ec7af2060..b2b895fa670e 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json @@ -3,42 +3,41 @@ "ConfigCode": "0x00", "EventName": "rx_ops_num", "BriefDescription": "The number of all operations received by the HHA", - "PublicDescription": "The number of all operations received by the HHA", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x01", "EventName": "rx_outer", "BriefDescription": "The number of all operations received by the HHA from another socket", - "PublicDescription": "The number of all operations received by the HHA from another socket", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x02", "EventName": "rx_sccl", "BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket", - "PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x03", "EventName": "rx_ccix", "BriefDescription": "Count of the number of operations that HHA has received from CCIX", - "PublicDescription": "Count of the number of operations that HHA has received from CCIX", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x4", "EventName": "rx_wbi", + "BriefDescription": "Count of the number of WriteBackI operations that HHA has received", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x5", "EventName": "rx_wbip", + "BriefDescription": "Count of the number of WriteBackIPtl operations that HHA has received", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x11", + "BriefDescription": "Count of the number of WriteThruIStash operations that HHA has received", "EventName": "rx_wtistash", "Unit": "hisi_sccl,hha" }, @@ -46,107 +45,114 @@ "ConfigCode": "0x1c", "EventName": "rd_ddr_64b", "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes", - "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x1d", "EventName": "wr_ddr_64b", "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes", - "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x1e", "EventName": "rd_ddr_128b", "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes", - "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x1f", "EventName": "wr_ddr_128b", "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes", - "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x20", "EventName": "spill_num", "BriefDescription": "Count of the number of spill operations that the HHA has sent", - "PublicDescription": "Count of the number of spill operations that the HHA has sent", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x21", "EventName": "spill_success", "BriefDescription": "Count of the number of successful spill operations that the HHA has sent", - "PublicDescription": "Count of the number of successful spill operations that the HHA has sent", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x23", "EventName": "bi_num", + "BriefDescription": "Count of the number of HHA BackInvalid operations", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x32", "EventName": "mediated_num", + "BriefDescription": "Count of the number of Mediated operations that the HHA has forwarded", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x33", "EventName": "tx_snp_num", + "BriefDescription": "Count of the number of Snoop operations that the HHA has sent", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x34", "EventName": "tx_snp_outer", + "BriefDescription": "Count of the number of Snoop operations that the HHA has sent to another socket", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x35", "EventName": "tx_snp_ccix", + "BriefDescription": "Count of the number of Snoop operations that the HHA has sent to CCIX", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x38", "EventName": "rx_snprspdata", + "BriefDescription": "Count of the number of SnprspData flit operations that HHA has received", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x3c", "EventName": "rx_snprsp_outer", + "BriefDescription": "Count of the number of SnprspData operations that HHA has received from another socket", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x40", "EventName": "sdir-lookup", + "BriefDescription": "Count of the number of HHA S-Dir lookup operations", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x41", "EventName": "edir-lookup", + "BriefDescription": "Count of the number of HHA E-Dir lookup operations", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x42", "EventName": "sdir-hit", + "BriefDescription": "Count of the number of HHA S-Dir hit operations", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x43", "EventName": "edir-hit", + "BriefDescription": "Count of the number of HHA E-Dir hit operations", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x4c", "EventName": "sdir-home-migrate", + "BriefDescription": "Count of the number of HHA S-Dir read home migrate operations", "Unit": "hisi_sccl,hha" }, { "ConfigCode": "0x4d", "EventName": "edir-home-migrate", + "BriefDescription": "Count of the number of HHA E-Dir read home migrate operations", "Unit": "hisi_sccl,hha" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json index e3479b65be9a..d83c22eb1d15 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json @@ -3,91 +3,78 @@ "ConfigCode": "0x00", "EventName": "rd_cpipe", "BriefDescription": "Total read accesses", - "PublicDescription": "Total read accesses", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x01", "EventName": "wr_cpipe", "BriefDescription": "Total write accesses", - "PublicDescription": "Total write accesses", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x02", "EventName": "rd_hit_cpipe", "BriefDescription": "Total read hits", - "PublicDescription": "Total read hits", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x03", "EventName": "wr_hit_cpipe", "BriefDescription": "Total write hits", - "PublicDescription": "Total write hits", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x04", "EventName": "victim_num", "BriefDescription": "l3c precharge commands", - "PublicDescription": "l3c precharge commands", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x20", "EventName": "rd_spipe", "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe", - "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x21", "EventName": "wr_spipe", "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe", - "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x22", "EventName": "rd_hit_spipe", "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C", - "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x23", "EventName": "wr_hit_spipe", "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C", - "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x29", "EventName": "back_invalid", "BriefDescription": "Count of the number of L3C back invalid operations", - "PublicDescription": "Count of the number of L3C back invalid operations", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x40", "EventName": "retry_cpu", "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations", - "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x41", "EventName": "retry_ring", "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations", - "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations", "Unit": "hisi_sccl,l3c" }, { "ConfigCode": "0x42", "EventName": "prefetch_drop", "BriefDescription": "Count of the number of prefetch drops from this L3C", - "PublicDescription": "Count of the number of prefetch drops from this L3C", "Unit": "hisi_sccl,l3c" } ] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index f4d1ca4d1493..bb3fa8a33496 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -36,9 +36,12 @@ 0x00000000410fd480,v1,arm/cortex-x2,core 0x00000000410fd490,v1,arm/neoverse-n2-v2,core 0x00000000410fd4f0,v1,arm/neoverse-n2-v2,core +0x00000000410fd830,v1,arm/neoverse-v3,core +0x00000000410fd8e0,v1,arm/neoverse-n3,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000460f0010,v1,fujitsu/a64fx,core +0x00000000460f0030,v1,fujitsu/monaka,core 0x00000000480fd010,v1,hisilicon/hip08,core 0x00000000500f0000,v1,ampere/emag,core 0x00000000c00fac30,v1,ampere/ampereone,core diff --git a/tools/perf/pmu-events/arch/arm64/recommended.json b/tools/perf/pmu-events/arch/arm64/recommended.json index 210afa856091..a3b4941ae90c 100644 --- a/tools/perf/pmu-events/arch/arm64/recommended.json +++ b/tools/perf/pmu-events/arch/arm64/recommended.json @@ -318,6 +318,11 @@ "BriefDescription": "Barrier speculatively executed, DMB" }, { + "EventCode": "0x7F", + "EventName": "CSDB_SPEC", + "BriefDescription": "Barrier Speculatively executed, CSDB." + }, + { "PublicDescription": "Exception taken, Other synchronous", "EventCode": "0x81", "EventName": "EXC_UNDEF", diff --git a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ali_drw.json index e21c469a8ef0..e21c469a8ef0 100644 --- a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json +++ b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ali_drw.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/metrics.json index bc865b374b6a..bc865b374b6a 100644 --- a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/metrics.json |