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path: root/Documentation/devicetree/bindings/clock/sunxi.txt
AgeCommit message (Expand)Author
2019-12-24dt-bindings: clocks: Convert Allwinner legacy clocks to schemasMaxime Ripard
2017-11-09dt-bindings: Remove leading zeros from bindings notationMarco Franchi
2016-05-12clk: sunxi: Add display and TCON0 clocks driverMaxime Ripard
2016-04-22clk: sunxi: Add TCON channel1 clockMaxime Ripard
2016-04-22clk: sunxi: Add PLL3 clockMaxime Ripard
2016-04-22dt-bindings: clk: sun5i: add DRAM gates compatibleMaxime Ripard
2016-04-22clk: sunxi: Add sun6i/8i display supportJean-Francois Moine
2016-02-25clk: sunxi: Add apb0 gates for H3Krzysztof Adamski
2016-02-02clk: sunxi: add bus gates for A83TVishnu Patekar
2016-02-02clk: sunxi: Add apb0 gates for A83TVishnu Patekar
2015-12-08clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]iChen-Yu Tsai
2015-12-08clk: sunxi: Add H3 clocks supportJens Kuske
2015-12-07clk: sunxi: Add DRAM gates support for sun4i-a10Chen-Yu Tsai
2015-12-01clk: sunxi: Add sun9i A80 cpus (cpu special) clock supportChen-Yu Tsai
2015-12-01clk: sunxi: Add sun9i A80 apbs gates supportChen-Yu Tsai
2015-11-20clk: sunxi: Add support for the H3 usb phy clocksReinder de Haan
2015-06-02clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCsHans de Goede
2015-03-21clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai
2015-02-23clk: sunxi: Add support for sun9i A80 USB clocks and resetsChen-Yu Tsai
2015-01-20clk: sunxi: Add driver for A80 MMC config clocks/resetsChen-Yu Tsai
2015-01-19clk: sunxi: Add mod0 and mmc module clock support for A80Chen-Yu Tsai
2015-01-14clk: sunxi: Rework MMC phase clocksMaxime Ripard
2014-12-21clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai
2014-11-23clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai
2014-11-23clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai
2014-11-11clk: sunxi: unify APB1 clockEmilio López
2014-10-21clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai
2014-10-21clk: sunxi: Add support for A80 basic bus clocksChen-Yu Tsai
2014-09-27clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai
2014-09-27clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard
2014-09-27clk: sunxi: Introduce mbus compatibleMaxime Ripard
2014-07-15clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai
2014-07-07clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai
2014-07-04clk: sunxi: Add A23 clocks supportChen-Yu Tsai
2014-06-11clk: sunxi: document PRCM clock compatible stringsBoris BREZILLON
2014-06-11clk: sunxi: document new A31 USB clock compatibleEmilio López
2014-02-18clk: sunxi: Add new clock compatiblesMaxime Ripard
2014-02-18clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai
2014-02-18clk: sunxi: Add support for PLL6 on the A31Maxime Ripard
2014-02-18clk: sunxi: Add USB clock register defintionsRoman Byshko
2014-02-03clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai
2013-12-28clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai
2013-12-28clk: sunxi: mod0 supportEmilio López
2013-12-28clk: sunxi: add PLL5 and PLL6 supportEmilio López
2013-12-28clk: sunxi: add gating support to PLL1Emilio López
2013-10-11Documentation: dt: Remove clock gates IDs list for Allwinner SoCsMaxime Ripard
2013-08-26clk: sunxi: Add Allwinner A20 gatesMaxime Ripard
2013-08-26clk: sunxi: Add A31 clocks supportMaxime Ripard
2013-08-26clk: sunxi: Add A10s gatesMaxime Ripard
2013-05-28clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard
generated by cgit (git 2.34.1) at 2024-05-02 09:38:41 +0000