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path: root/drivers/clk/clk-composite.c
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2023-06-12clk: composite: Fix handling of high clock ratesSebastian Reichel
ULONG_MAX is used by a few drivers to figure out the highest available clock rate via clk_round_rate(clk, ULONG_MAX). Since abs() takes a signed value as input, the current logic effectively calculates with ULONG_MAX = -1, which results in the worst parent clock being chosen instead of the best one. For example on Rockchip RK3588 the eMMC driver tries to figure out the highest available clock rate. There are three parent clocks available resulting in the following rate diffs with the existing logic: GPLL: abs(18446744073709551615 - 1188000000) = 1188000001 CPLL: abs(18446744073709551615 - 1500000000) = 1500000001 XIN24M: abs(18446744073709551615 - 24000000) = 24000001 As a result the clock framework will promote a maximum supported clock rate of 24 MHz, even though 1.5GHz are possible. With the updated logic any casting between signed and unsigned is avoided and the numbers look like this instead: GPLL: 18446744073709551615 - 1188000000 = 18446744072521551615 CPLL: 18446744073709551615 - 1500000000 = 18446744072209551615 XIN24M: 18446744073709551615 - 24000000 = 18446744073685551615 As a result the parent with the highest acceptable rate is chosen instead of the parent clock with the lowest one. Cc: stable@vger.kernel.org Fixes: 49502408007b ("mmc: sdhci-of-dwcmshc: properly determine max clock on Rockchip") Tested-by: Christopher Obbard <chris.obbard@collabora.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230526171057.66876-2-sebastian.reichel@collabora.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-15clk: Stop forwarding clk_rate_requests to the parentMaxime Ripard
If the clock cannot modify its rate and has CLK_SET_RATE_PARENT, clk_mux_determine_rate_flags(), clk_core_round_rate_nolock() and a number of drivers will forward the clk_rate_request to the parent clock. clk_core_round_rate_nolock() will pass the pointer directly, which means that we pass a clk_rate_request to the parent that has the rate, min_rate and max_rate of the child, and the best_parent_rate and best_parent_hw fields will be relative to the child as well, so will point to our current clock and its rate. The most common case for CLK_SET_RATE_PARENT is that the child and parent clock rates will be equal, so the rate field isn't a worry, but the other fields are. Similarly, if the parent clock driver ever modifies the best_parent_rate or best_parent_hw, this will be applied to the child once the call to clk_core_round_rate_nolock() is done. best_parent_hw is probably not going to be a valid parent, and best_parent_rate might lead to a parent rate change different to the one that was initially computed. clk_mux_determine_rate_flags() and the affected drivers will copy the request before forwarding it to the parents, so they won't be affected by the latter issue, but the former is still going to be there and will lead to erroneous data and context being passed to the various clock drivers in the same sub-tree. Let's create two new functions, clk_core_forward_rate_req() and clk_hw_forward_rate_request() for the framework and the clock providers that will copy a request from a child clock and update the context to match the parent's. We also update the relevant call sites in the framework and drivers to use that new function. Let's also add a test to make sure we avoid regressions there. Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220816112530.1837489-22-maxime@cerno.tech Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-03clk: composite: Fix 'switching' to same clockAlexander Stein
During commit 6594988fd625 ("clk: composite: Use rate_ops.determine_rate when also a mux is available") setting req->best_parent_hw got lost, so best_parent_hw stays NULL during switch to the same parent. This results in the (debug) message: clk_calc_new_rates: lcdif_pixel not gated but wants to reparent and the following rate change is dropped. Fixes: 6594988fd625 ("clk: composite: Use rate_ops.determine_rate when also a mux is available") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103122441.3208576-1-alexander.stein@ew.tq-group.com Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-02Merge branches 'clk-composite-determine-fix', 'clk-allwinner', 'clk-amlogic' ↵Stephen Boyd
and 'clk-samsung' into clk-next * clk-composite-determine-fix: clk: composite: Use rate_ops.determine_rate when also a mux is available clk: composite: Also consider .determine_rate for rate + mux composites * clk-allwinner: clk: sunxi: sun8i-apb0: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: sun6i-ar100: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: sun6i-apb0-gates: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: sun6i-apb0: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun9i-a80-de: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun9i-a80: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun8i-de2: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun8i-a83t: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun50i-h6: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun50i-a64: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: clk-mod0: Make use of the helper function devm_platform_ioremap_resource() dt-bindings: clocks: Fix typo in the H6 compatible clk: sunxi-ng: Use a separate lock for each CCU instance clk: sunxi-ng: Prevent unbinding CCUs via sysfs clk: sunxi-ng: Unregister clocks/resets when unbinding clk: sunxi-ng: Add machine dependency to A83T CCU clk: sunxi-ng: mux: Remove unused 'reg' field * clk-amlogic: clk: meson: meson8b: Make the video clock trees mutable clk: meson: meson8b: Initialize the HDMI PLL registers clk: meson: meson8b: Add the HDMI PLL M/N parameters clk: meson: meson8b: Add the vid_pll_lvds_en gate clock clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel clk: meson: meson8b: Export the video clocks * clk-samsung: clk: samsung: describe drivers in Kconfig clk: samsung: exynos5433: update apollo and atlas clock probing clk: samsung: add support for CPU clocks clk: samsung: Introduce Exynos850 clock driver dt-bindings: clock: Document Exynos850 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos850 CMU clk: samsung: clk-pll: Implement pll0831x PLL type clk: samsung: clk-pll: Implement pll0822x PLL type clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource() clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource() clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource() clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()
2021-10-18clk: composite: Use rate_ops.determine_rate when also a mux is availableMartin Blumenstingl
Update clk_composite_determine_rate() to use rate_ops.determine_rate when available in combination with a mux. So far clk_divider_ops provide both, .round_rate and .determine_rate. Removing the former would make clk-composite fail silently for example on Rockchip platforms (which heavily use composite clocks). Add support for using rate_ops.determine_rate when either rate_ops.round_rate is not available or both (.round_rate and .determine_rate) are provided. Suggested-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211016105022.303413-3-martin.blumenstingl@googlemail.com Tested-by: Alex Bee <knaerzche@gmail.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-18clk: composite: Also consider .determine_rate for rate + mux compositesMartin Blumenstingl
Commit 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") switches clk_divider_ops to implement .determine_rate by default. This breaks composite clocks with multiple parents because clk-composite.c does not use the special handling for mux + divider combinations anymore (that was restricted to rate clocks which only implement .round_rate, but not .determine_rate). Alex reports: This breaks lot of clocks for Rockchip which intensively uses composites, i.e. those clocks will always stay at the initial parent, which in some cases is the XTAL clock and I strongly guess it is the same for other platforms, which use composite clocks having more than one parent (e.g. mediatek, ti ...) Example (RK3399) clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot. It will always stay at this parent, even if the mmc driver sets a rate of 200 MHz (fails, as the nature of things), which should switch it to any of its possible parent PLLs defined in mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which never happens. Restore the original behavior by changing the priority of the conditions inside clk-composite.c. Now the special rate + mux case (with rate_ops having a .round_rate - which is still the case for the default clk_divider_ops) is preferred over rate_ops which have .determine_rate defined (and not further considering the mux). Fixes: 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") Reported-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211016105022.303413-2-martin.blumenstingl@googlemail.com Tested-by: Alex Bee <knaerzche@gmail.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14clk: composite: export clk_register_compositeMiles Chen
To support module build of mediatek clk drivers, it is necessary to export clk_register_composite. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210901222526.31065-2-miles.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: composite: add devm_clk_hw_register_composite_pdata()Michael Walle
This will simplify drivers which would only unregister the clk in their remove() op. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201105192746.19564-3-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-22clk: composite: Export clk_hw_register_composite()Anson Huang
Export clk_hw_register_composite() to support user built as module. ERROR: modpost: "clk_hw_register_composite" [drivers/clk/imx/mxc-clk.ko] undefined! Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-28clk: composite: add _register_composite_pdata() variantsMichael Walle
Add support for the new way of specifying the clock parents. Add the two new functions clk_hw_register_composite_pdata() clk_register_composite_pdata() to let the driver provide parent_data instead of the parent_names. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lkml.kernel.org/r/20200102231101.11834-1-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-22clk: Add clk_hw_unregister_composite helper function definitionManivannan Sadhasivam
This function has been delcared but not defined anywhere. Hence, this commit adds definition for it. Fixes: 49cb392d3639 ("clk: composite: Add hw based registration APIs") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lkml.kernel.org/r/20191115162901.17456-3-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-22clk: Zero init clk_init_data in helpersManivannan Sadhasivam
The clk_init_data struct needs to be initialized to zero for the new parent_map implementation to work correctly. Otherwise, the member which is available first will get processed. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lkml.kernel.org/r/20191115162901.17456-2-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16clk: composite: Drop unused clk.h includeStephen Boyd
This include isn't used. Drop it. Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815042500.9519-1-sboyd@kernel.org
2019-04-26clk: Remove CLK_IS_BASIC clk flagStephen Boyd
This flag was historically used to indicate that a clk is a "basic" type of clk like a mux, divider, gate, etc. This never turned out to be very useful though because it was hard to cleanly split "basic" clks from other clks in a system. This one flag was a way for type introspection and it just didn't scale. If anything, it was used by the TI clk driver to indicate that a clk_hw wasn't contained in the SoC specific clk structure. We can get rid of this define now that TI is finding those clks a different way. Cc: Tero Kristo <t-kristo@ti.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: <linux-mips@vger.kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: <linux-pwm@vger.kernel.org> Cc: <linux-amlogic@lists.infradead.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: Tag basic clk types with SPDXStephen Boyd
These are all GPL-2.0 files per the existing license text. Replace the boiler plate with the tag. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2016-04-21Merge branch 'clk-hw-register' (early part) into clk-nextStephen Boyd
* 'clk-hw-register' (early part): clk: fixed-rate: Add hw based registration APIs clk: gpio: Add hw based registration APIs clk: composite: Add hw based registration APIs clk: fractional-divider: Add hw based registration APIs clk: fixed-factor: Add hw based registration APIs clk: mux: Add hw based registration APIs clk: gate: Add hw based registration APIs clk: divider: Add hw based registration APIs clkdev: Add clk_hw based registration APIs clk: Add clk_hw OF clk providers clk: Add {devm_}clk_hw_{register,unregister}() APIs clkdev: Remove clk_register_clkdevs()
2016-04-21Merge branch 'clk-composite-unregister' into clk-nextStephen Boyd
* clk-composite-unregister: clk: composite: Add unregister function
2016-04-21clk: composite: Add unregister functionMaxime Ripard
The composite clock didn't have any unregistration function, which forced us to use clk_unregister directly on it. While it was already not great from an API point of view, it also meant that we were leaking the clk_composite structure allocated in clk_register_composite. Add a clk_unregister_composite function to fix this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19clk: composite: Add hw based registration APIsStephen Boyd
Add registration APIs in the clk composite code to return struct clk_hw pointers instead of struct clk pointers. This way we hide the struct clk pointer from providers unless they need to use consumer facing APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15clk: Add clk_composite_set_rate_and_parentFinley Xiao
When changing the clock-rate, currently a new parent is set first and a divider adapted thereafter. This may result in the clock-rate overflowing its target rate for a short time if the new parent has a higher rate than the old parent. While this often doesn't produce negative effects, it can affect components in a voltage-scaling environment, like the GPU on the rk3399 socs, where the voltage than simply is to low for the temporarily to high clock rate. For general clock hirarchies this may need more extensive adaptions to the common clock-framework, but at least for composite clocks having both parent and rate settings it is easy to create a short-term solution to make sure the clock-rate does not overflow the target. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: Convert basic types to clk_hw based provider APIsStephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd
Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()Stephen Boyd
Mostly converted with the following semantic patch: @@ struct clk_hw *E; @@ -__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E) Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chao Xie <chao.xie@marvell.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27clk: fix some determine_rate implementationsBoris Brezillon
Some determine_rate implementations are not returning an error when they failed to adapt the rate according to the rate request. Fix them so that they return an error instead of silently returning 0. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14clk: basic-types: Remove useless allocation failure printksStephen Boyd
Printing an error on kmalloc() failures is unnecessary. Remove the print and use *ptr in sizeof() for future-proof code. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05clk: make strings in parent name arrays constSascha Hauer
The clk functions and structs declare the parent_name arrays as 'const char **parent_names' which means the parent name strings are const, but the array itself is not. Use 'const char * const * parent_names' instead which also makes the array const. This allows us to put the parent_name arrays into the __initconst section. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [sboyd@codeaurora.org: Squelch 80-character checkpatch warnings] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-02-18clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas
The change in the clk API to return a per-user clock instance, moved the clock state to struct clk_core so now the struct clk_hw .core field is used instead of .clk for most operations. So for hardware clocks that needs to share the same clock state, both the .core and .clk pointers have to be assigned but currently only the .clk is set. This leads to NULL pointer dereference when the operations try to access the hw clock .core. For example, the composite clock rate and mux components didn't have a .core set which leads to this error: Unable to handle kernel NULL pointer dereference at virtual address 00000034 pgd = c0004000 [00000034] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) task: ee480000 ti: ee488000 task.ti: ee488000 PC is at clk_mux_determine_rate_flags+0x14/0x19c LR is at __clk_mux_determine_rate+0x24/0x2c pc : [<c03a355c>] lr : [<c03a3734>] psr: a0000113 sp : ee489ce8 ip : ee489d84 fp : ee489d84 r10: 0000005c r9 : 00000001 r8 : 016e3600 r7 : 00000000 r6 : 00000000 r5 : ee442200 r4 : ee440c98 r3 : ffffffff r2 : 00000000 r1 : 016e3600 r0 : ee440c98 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 4000406a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xee488210) Stack: (0xee489ce8 to 0xee48a000) 9ce0: 00000000 ffffffff 60000113 ee440c98 ee442200 00000000 9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84 9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea 9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000 9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84 9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff 9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4 9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700 9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64 9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54 9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0 9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010 9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c 9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000 9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40 9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4 9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944 9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000 9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec 9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424 9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006 9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000 9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [<c03a355c>] (clk_mux_determine_rate_flags) from [<c03a3734>] (__clk_mux_determine_rate+0x24/0x2c) [<c03a3734>] (__clk_mux_determine_rate) from [<c03a5798>] (clk_composite_determine_rate+0xbc/0x238) [<c03a5798>] (clk_composite_determine_rate) from [<c03a11a0>] (clk_core_round_rate_nolock+0x5c/0x9c) [<c03a11a0>] (clk_core_round_rate_nolock) from [<c03a1228>] (__clk_round_rate+0x38/0x40) [<c03a1228>] (__clk_round_rate) from [<c03a1c1c>] (clk_round_rate+0x20/0x38) [<c03a1c1c>] (clk_round_rate) from [<c03d6ce4>] (max98090_dai_set_sysclk+0x34/0x118) [<c03d6ce4>] (max98090_dai_set_sysclk) from [<c03c797c>] (snd_soc_dai_set_sysclk+0x38/0x80) [<c03c797c>] (snd_soc_dai_set_sysclk) from [<c03db8ac>] (snow_late_probe+0x24/0x48) [<c03db8ac>] (snow_late_probe) from [<c03c8f08>] (snd_soc_register_card+0xf04/0x1070) [<c03c8f08>] (snd_soc_register_card) from [<c03d4398>] (devm_snd_soc_register_card+0x30/0x64) [<c03d4398>] (devm_snd_soc_register_card) from [<c03db824>] (snow_probe+0x68/0xcc) [<c03db824>] (snow_probe) from [<c0299c7c>] (platform_drv_probe+0x48/0x98) [<c0299c7c>] (platform_drv_probe) from [<c0298858>] (driver_probe_device+0x114/0x234) [<c0298858>] (driver_probe_device) from [<c0298a04>] (__driver_attach+0x8c/0x90) [<c0298a04>] (__driver_attach) from [<c02971d4>] (bus_for_each_dev+0x54/0x88) [<c02971d4>] (bus_for_each_dev) from [<c0298044>] (bus_add_driver+0xd8/0x1cc) [<c0298044>] (bus_add_driver) from [<c0299024>] (driver_register+0x78/0xf4) [<c0299024>] (driver_register) from [<c0008944>] (do_one_initcall+0x80/0x1d0) [<c0008944>] (do_one_initcall) from [<c066bd44>] (kernel_init_freeable+0x10c/0x1d8) [<c066bd44>] (kernel_init_freeable) from [<c0481940>] (kernel_init+0x8/0xe4) [<c0481940>] (kernel_init) from [<c000e680>] (ret_from_fork+0x14/0x34) Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034) The changes were made using the following cocinelle semantic patch: @i@ @@ @depends on i@ identifier dst; @@ - dst->clk = hw->clk; + __clk_hw_set_clk(dst, hw); @depends on i@ identifier dst; @@ - dst->hw.clk = hw->clk; + __clk_hw_set_clk(&dst->hw, hw); Fixes: 035a61c314eb3 ("clk: Make clk API return per-user struct clk instances") Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-02clk: Add rate constraints to clocksTomeu Vizoso
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
2014-12-03clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-07-13clk: composite: improve rate_hw sanity check logicMike Turquette
The function pointer population and sanity checking logic got a bit ugly with the advent of the .determine_rate callback. Clean it up. Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13clk: composite: allow read-only clocksHeiko Stübner
This allows readl-only composite clocks by making mux_ops->set_parent and divider_ops->round_rate/set_rate optional. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13clk: composite: support determine_rate using rate_ops->round_rate + ↵Boris BREZILLON
mux_ops->set_parent In case the rate_hw does not implement determine_rate, but only round_rate we fallback to best_parent selection if mux_hw is present and support reparenting. This also fixes a rate calculation problem when using the standard div and mux ops, as in this case currently only the mux->determine_rate is used in the composite rate calculation. So when for example the composite clock has two parents at 600 and 800MHz, the requested rate is 75MHz, which the divider could provide, without this change the rate would be set 600MHz ignoring the divider completely. This may be way out of spec for the component. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [heiko@sntech.de: fixed output return a rate instead of the diff] Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Tested-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-15clk: composite: pass mux_hw into determine_rateMike Turquette
The composite clock's .determine_rate implementation can call the underyling .determine_rate callback corresponding to rate_hw or the underlying .determine_rate callback corresponding to mux_hw. In both cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into the correct callback. Reported-by: Lemon Dai <dailemon.gl@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-11-10clk: composite: .determine_rate supportEmilio López
This commit adds .determine_rate support to the composite clock. It will use the .determine_rate callback from the rate component if available, and fall back on the mux component otherwise. This allows composite clocks to enjoy the benefits of automatic clock reparenting. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-12clk: composite: allow fixed rates & fixed dividersMike Turquette
The composite clock assumes that any clock implementing the .recalc_rate callback will also implement .round_rate and .set_rate. This is not always true; the basic fixed-rate clock will only implement .recalc_rate and a fixed-divider clock may choose to implement .recalc_rate and .round_rate but not .set_rate. Fix this by conditionally registering .round_rate and .set_rate callbacks based on the rate_ops passed in to clk_composite_register. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12clk: composite: rename 'div' references to 'rate'Mike Turquette
Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-03-26clk: Add composite clock typePrashant Gaikwad
Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>