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path: root/drivers/cxl/core/port.c
AgeCommit message (Expand)Author
2024-04-29cxl: Fix cxl_endpoint_get_perf_coordinate() support for RCHDave Jiang
2024-04-08cxl: Add checks to access_coordinate calculation to fail missing dataDave Jiang
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang
2024-04-08cxl: Fix retrieving of access_coordinates in PCIe pathDave Jiang
2024-04-05cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates()Dave Jiang
2024-03-13Merge branch 'for-6.9/cxl-einj' into for-6.9/cxlDan Williams
2024-03-12cxl/core: Add CXL EINJ debugfs filesBen Cheatham
2024-03-12cxl: Set cxlmd->endpoint before adding port deviceDave Jiang
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang
2024-01-05Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang
2024-01-05cxl: Introduce put_cxl_root() helperDave Jiang
2024-01-04cxl/port: Fix missing target list lockDan Williams
2024-01-04cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying
2023-12-22cxl: Add helper function that calculate performance data for downstream portsDave Jiang
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang
2023-12-22cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang
2023-12-07cxl/hdm: Fix dpa translation lockingDan Williams
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang
2023-10-27cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang
2023-10-27PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter
2023-10-27cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter
2023-10-27cxl/port: Pre-initialize component register mappingsRobert Richter
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter
2023-10-27cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter
2023-10-27cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams
2023-10-06cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams
2023-09-22cxl/port: Fix cxl_test register enumeration regressionDan Williams
2023-09-15cxl/port: Quiet warning messages from the cxl_test environmentDan Williams
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams
2023-06-25cxl/memdev: Formalize endpoint port linkageDan Williams
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams
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