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path: root/drivers/gpu/drm/amd/include/asic_reg/gc
AgeCommit message (Expand)Author
2020-01-30drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for ArcturusJoseph Greathouse
2020-01-22drm/amdgpu: add EDC counter registers of gc for ArcturusDennis Li
2020-01-14drm/amdgpu: add defines for DF and TCP HashingJoseph Greathouse
2019-12-23drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support ArcturusJames Zhu
2019-10-15drm/amd/include: add register define for VML2 and ATCL2Dennis Li
2019-08-02drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan
2019-07-31drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li
2019-07-31drm/amd/include: add bitfield define for EDC registersDennis Li
2019-06-20drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang
2019-05-24drm/amdgpu: add EDC counter registerJames Zhu
2018-10-10drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou
2018-09-10drm/amd/include: update the bitfield define for PF_MAX_REGIONShaoyun Liu
2018-03-21drm/amd/include: Add ip header files for vega12.Feifei Xu
2018-03-07drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header filesTom St Denis
2017-12-13drm/amdgpu: remove some old gc 9.x registersAlex Deucher
2017-12-06drm/amd/include:cleanup raven1 gc header files.Feifei Xu
2017-12-06drm/amd/include:cleanup vega10 gc header files.Feifei Xu
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