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path: root/drivers/gpu/drm/i915/display/intel_dpll.c
AgeCommit message (Expand)Author
2024-09-03drm/i915/pps: convert intel_pps.[ch] to struct intel_displayJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to DPLL_MDJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to DPLLJani Nikula
2024-04-30drm/i915/dpio: Extract vlv_dpio_phy_regs.hVille Syrjälä
2024-04-30drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä
2024-04-30drm/i915/dpio: s/pipe/ch/Ville Syrjälä
2024-04-30drm/i915/dpio: s/port/ch/Ville Syrjälä
2024-04-30drm/i915/dpio: Rename some variablesVille Syrjälä
2024-04-30drm/i915/dpio: Remove pointless variables from vlv/chv DPLL codeVille Syrjälä
2024-04-30drm/i915/dpio: Fix VLV DPIO PLL register dword numberingVille Syrjälä
2024-04-30drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/Ville Syrjälä
2024-04-30drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/Ville Syrjälä
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä
2024-04-17drm/i915: Add local DPLL 'hw_state' variablesVille Syrjälä
2024-04-17drm/i915: s/pipe_config/crtc_state/ in legacy PLL codeVille Syrjälä
2024-04-17drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()Ville Syrjälä
2024-04-17drm/i915: Modernize i9xx_pll_refclk()Ville Syrjälä
2024-04-17drm/i915: Inline {i9xx,ilk}_update_pll_dividers()Ville Syrjälä
2024-04-17drm/i915: Extract {i9xx,i8xx,ilk,vlv,chv}_dpll()Ville Syrjälä
2024-04-17drm/i915: Extract i965_dpll_md()Ville Syrjälä
2024-04-17drm/i915: Extract i9xx_dpll_get_hw_state()Ville Syrjälä
2024-04-17drm/i915: Extract ilk_dpll_compute_fp()Ville Syrjälä
2024-04-17drm/i915: Extract ilk_fb_cb_factor()Ville Syrjälä
2023-11-17drm/i915: convert vlv_dpio_read()/write() from pipe to phyJani Nikula
2023-11-17drm/i915: move *_crtc_clock_get() to intel_dpll.cJani Nikula
2023-10-29drm/i915/display: Abstract C10/C20 pll calculationLucas De Marchi
2023-10-12drm/i915/display: Use correct method to free crtc_stateSuraj Kandpal
2023-08-24drm/i915: Fully populate crtc_state->dpllVille Syrjälä
2023-08-24drm/i915: Don't warn about zero N/P in *_calc_dpll_params()Ville Syrjälä
2023-06-07drm/i915/dpll: drop unused but set variables bestn and bestm1Jani Nikula
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula
2023-04-28drm/i915/mtl: C20 port clock calculationMika Kahola
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada
2023-01-18drm/i915: move chv_dpll_md and bxt_phy_grc to display sub-struct under stateJani Nikula
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula
2022-11-03drm/i915/dpio: un-inline the vlv phy/channel mapping functionsJani Nikula
2022-09-13drm/i915: Fix TV encoder clock computationVille Syrjälä
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä
2022-09-08drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()Ville Syrjälä
2022-09-08drm/i915: Do .crtc_compute_clock() earlierVille Syrjälä
2022-08-31drm/i915: move vbt to display.vbtJani Nikula
2022-08-29drm/i915: move dpll_funcs to display.funcsJani Nikula
2022-05-31drm/i915: Clean up DPLL related debugsVille Syrjälä
2022-05-31drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä
2022-04-25drm/i915: Add crtc .crtc_get_shared_dpll()Ville Syrjälä
2022-04-25drm/i915: Split out dg2_crtc_compute_clock()Ville Syrjälä
2022-04-25drm/i915: Clear the dpll_hw_state when disabling a pipeVille Syrjälä
2022-04-25drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()Ville Syrjälä
2022-04-25drm/i915: Move stuff into intel_dpll_crtc_compute_clock()Ville Syrjälä
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