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path: root/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
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2022-06-16drm/sun4i: sun8i-hdmi-phy: Group PHY ops functions by generationSamuel Holland
Now that the PHY ops are separated, sort them topologically, with the common sun8i_hdmi_phy_set_polarity helper at the top. No function contents are changed in this commit. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-7-samuel@sholland.org
2022-06-16drm/sun4i: sun8i-hdmi-phy: Separate A83T and H3 PHY opsSamuel Holland
Since the driver already needs to support multiple sets of ops, we can drop the mid-layer used by the A83T and H3 PHYs. They share only a small amount of code; factor this out as sun8i_hdmi_phy_set_polarity. For clarity, this commit keeps the existing function order. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-6-samuel@sholland.org
2022-06-16drm/sun4i: sun8i-hdmi-phy: Support multiple custom PHY opsSamuel Holland
The D1 SoC comes with a new custom HDMI PHY, which does not share any registers with the existing custom PHY. So it needs a new set of ops. Instead of providing a flag in the variant structure, provide the ops themselves. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-5-samuel@sholland.org
2022-06-16drm/sun4i: sun8i-hdmi-phy: Used device-managed clocks/resetsSamuel Holland
Now that the HDMI PHY is using a platform driver, it can use device- managed resources. Use these, as well as the dev_err_probe helper, to simplify the probe function and get rid of the remove function. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-4-samuel@sholland.org
2022-06-16drm/sun4i: sun8i-hdmi-phy: Use devm_platform_ioremap_resourceSamuel Holland
The struct resource is not used for anything else, so we can simplify the code a bit by using the helper function. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-3-samuel@sholland.org
2022-06-16drm/sun4i: sun8i-hdmi-phy: Use of_device_get_match_dataSamuel Holland
Now that the HDMI PHY is using a platform driver, we can use the usual helper function for getting the variant structure. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-2-samuel@sholland.org
2022-04-19drm: bridge: dw_hdmi: add reset function for PHY GEN1Sandor Yu
PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2, and active low reset control for PHY GEN1. Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset. Add dw_hdmi_phy_gen1_reset function for PHY GEN1. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/e0b3be2d63fe3e95246fb8b8b0dcd57415b29e04.1649989179.git.Sandor.yu@nxp.com
2022-01-11drm/sun4i: dw-hdmi: Fix missing put_device() call in sun8i_hdmi_phy_getMiaoqian Lin
The reference taken by 'of_find_device_by_node()' must be released when not needed anymore. Add the corresponding 'put_device()' in the error handling path. Fixes: 9bf3797796f5 ("drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20220107083633.20843-1-linmq006@gmail.com
2021-10-06drm/sun4i: dw-hdmi: Fix HDMI PHY clock setupJernej Skrabec
Recent rework, which made HDMI PHY driver a platform device, inadvertely reversed clock setup order. HW is very touchy about it. Proper way is to handle controllers resets and clocks first and HDMI PHYs second. Currently, without this fix, first mode set completely fails (nothing on HDMI monitor) on H3 era PHYs. On H6, it still somehow work. Move HDMI PHY reset & clocks handling to sun8i_hdmi_phy_init() which will assure that code is executed after controllers reset & clocks are handled. Additionally, add sun8i_hdmi_phy_deinit() which will deinit them at controllers driver unload. Tested on A64, H3, H6 and R40. Fixes: 9bf3797796f5 ("drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210915175836.3158839-1-jernej.skrabec@gmail.com Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2021-06-07drm/sun4i: dw-hdmi: Make HDMI PHY into a platform deviceSaravana Kannan
On sunxi boards that use HDMI output, HDMI device probe keeps being avoided indefinitely with these repeated messages in dmesg: platform 1ee0000.hdmi: probe deferral - supplier 1ef0000.hdmi-phy not ready There's a fwnode_link being created with fw_devlink=on between hdmi and hdmi-phy nodes, because both nodes have 'compatible' property set. Fw_devlink code assumes that nodes that have compatible property set will also have a device associated with them by some driver eventually. This is not the case with the current sun8i-hdmi driver. This commit makes sun8i-hdmi-phy into a proper platform device and fixes the display pipeline probe on sunxi boards that use HDMI. More context: https://lkml.org/lkml/2021/5/16/203 Signed-off-by: Saravana Kannan <saravanak@google.com> Signed-off-by: Ondrej Jirman <megous@megous.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210607085836.2827429-1-megous@megous.com
2021-02-10drm/sun4i: Fix H6 HDMI PHY configurationJernej Skrabec
As it turns out, vendor HDMI PHY driver for H6 has a pretty big table of predefined values for various pixel clocks. However, most of them are not useful/tested because they come from reference driver code. Vendor PHY driver is concerned with only few of those, namely 27 MHz, 74.25 MHz, 148.5 MHz, 297 MHz and 594 MHz. These are all frequencies for standard CEA modes. Fix sun50i_h6_cur_ctr and sun50i_h6_phy_config with the values only for aforementioned frequencies. Table sun50i_h6_mpll_cfg doesn't need to be changed because values are actually frequency dependent and not so much SoC dependent. See i.MX6 documentation for explanation of those values for similar PHY. Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY") Tested-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210209175900.7092-5-jernej.skrabec@siol.net
2020-08-18drm/sun4i: Constify static structsRikard Falkeborn
A number of static variables are not modified and can be made const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20200804215337.54594-1-rikard.falkeborn@gmail.com
2020-06-23drm: bridge: dw-hdmi: Pass drm_display_info to dw_hdmi_support_scdc()Laurent Pinchart
To prepare for making connector creation optional in the driver, pass the drm_display_info explicitly to dw_hdmi_support_scdc(). The pointer is passed to the callers where required, particularly to the dw_hdmi_phy_ops .init() function. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200526011505.31884-19-laurent.pinchart+renesas@ideasonboard.com
2020-06-23drm: bridge: dw-hdmi: Constify mode argument to dw_hdmi_phy_ops .init()Laurent Pinchart
The PHY .init() must not modify the mode it receives. Make the pointer const to enfore that. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200526011505.31884-17-laurent.pinchart+renesas@ideasonboard.com
2019-05-16drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHzJernej Skrabec
Vendor provided documentation says that EMP bits should be set to 3 for pixel clocks greater than 148.5 MHz. Fix that. Cc: stable@vger.kernel.org # 4.17+ Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190514204337.11068-3-jernej.skrabec@siol.net
2019-05-16drm/sun4i: Fix sun8i HDMI PHY clock initializationJernej Skrabec
Current code initializes HDMI PHY clock driver before reset line is deasserted and clocks enabled. Because of that, initial readout of clock divider is incorrect (0 instead of 2). This causes any clock rate with divider 1 (register value 0) to be set incorrectly. Fix this by moving initialization of HDMI PHY clock driver after reset line is deasserted and clocks enabled. Cc: stable@vger.kernel.org # 4.17+ Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190514204337.11068-2-jernej.skrabec@siol.net
2018-11-05drm/sun4i: Add support for H6 HDMI PHYJernej Skrabec
H6 has Synopsys DWC HDMI 2.0 TX PHY. There is no freely available documentation for it, only code found in BSP kernel. However, judging by the code, PHY is very similar to older Synopsys HDMI PHY described in i.MX6 documentation. Most registers seem to be the same. According to i.MX6 documentation, mpll settings are based on pixel clock and are not specific to each SoC. Because of that, mpll table in this commit is based on that documentation and not on BSP code. Other PHY settings were derived from BSP PHY driver code. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-23-jernej.skrabec@siol.net
2018-11-05drm/sun4i: Add support for Synopsys HDMI PHYJernej Skrabec
Currently sun8i-hdmi-phy driver supports only custom PHYs connected to DW HDMI controller. Since newest Allwinner SoCs have unmodified Synopsys PHY, driver has to be reorganized to support them. Variant structure is expanded to allow differentiation between custom and Sysnopsys PHYs and to hold Synopsys PHY settings. Since DW HDMI bridge platform data has different fields for custom and Sysnopsys PHY, function sun8i_hdmi_phy_get_ops() is replaced with sun8i_hdmi_phy_set_ops(). Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-22-jernej.skrabec@siol.net
2018-11-05drm/sun4i: dw-hdmi-phy: Reorder quirks by familyJernej Skrabec
Currently, quirks and compatibles are sorted alphabetically. However, they should be sorted by family release date and then alphabetically. Fix that by moving A64 quirks and compatible to bottom. No functional change is made. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-21-jernej.skrabec@siol.net
2018-11-05drm/sun4i: Not all DW HDMI controllers has scrambled addressesJernej Skrabec
Currently supported Allwinner SoCs with DW HDMI controller have scrambled addresses and read lock. However, that is not true in general. For example, A80 and H6 have normal addresses and normal read access. Move code for unscrambling addresses and unlocking read access to it's own function and call it from init function. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-16-jernej.skrabec@siol.net
2018-09-27BackMerge v4.19-rc5 into drm-nextDave Airlie
Sean Paul requested an -rc5 backmerge from some sun4i fixes. Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-09-19drm/sun4i: add support for R40 HDMI PHYIcenowy Zheng
The R40 SoC has a HDMI PHY that is possible to mux two video PLLs. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180916043409.62374-4-icenowy@aosc.io
2018-09-19drm: sun4i: drop second PLL from A64 HDMI PHYIcenowy Zheng
The A64 HDMI PHY seems to be not able to use the second video PLL as clock parent in experiments. Drop the support for the second PLL from A64 HDMI PHY driver. Fixes: b46e2c9f5f64 ("drm/sun4i: Add support for A64 HDMI PHY") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180916043409.62374-2-icenowy@aosc.io
2018-06-27drm/sun4i: Add support for A64 HDMI PHYJernej Skrabec
PHY is the same as in H3, except it can switch between two clock parents. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-21-jernej.skrabec@siol.net
2018-06-27drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driverJernej Skrabec
Expand HDMI PHY clock driver to support second clock parent. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-20-jernej.skrabec@siol.net
2018-06-27drm/sun4i: DW HDMI PHY: Add support for second PLLJernej Skrabec
Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select between two clock parents. Add code which reads second PLL from DT. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-19-jernej.skrabec@siol.net
2018-06-27drm/sun4i: Don't change clock bits in DW HDMI PHY driverJernej Skrabec
DW HDMI PHY driver and PHY clock driver share same registers. Make sure that DW HDMI PHY setup code doesn't change any clock related bits. During initialization, set PHY PLL parent bit to 0. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-18-jernej.skrabec@siol.net
2018-06-27drm/sun4i: Enable DW HDMI PHY clockJernej Skrabec
Current DW HDMI PHY code never prepares and enables PHY clock after it is created. It's just used as it is. This may work in some cases, but it's clearly wrong. Fix it by adding proper calls to enable/disable PHY clock. Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-17-jernej.skrabec@siol.net
2018-03-02drm/sun4i: Add support for H3 HDMI PHY variantJernej Skrabec
While A83T HDMI PHY seems to be just customized Synopsys HDMI PHY, H3 HDMI PHY is completely custom PHY. However, they still have many things in common like clock and reset setup, setting sync polarity and more. Add support for H3 HDMI PHY variant. While documentation exists for this PHY variant, it doesn't go in great details. Because of that, almost all settings are copied from BSP linux 4.4. Interestingly, those settings are slightly different to those found in a older BSP with Linux 3.4. For now, no user visible difference was found between them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-13-jernej.skrabec@siol.net
2018-03-02drm/sun4i: Move and expand DW HDMI PHY register macrosJernej Skrabec
DW HDMI PHY macros are moved to header file and expanded with the registers present on newer SoCs like H3 and H5. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-12-jernej.skrabec@siol.net
2018-03-02drm/sun4i: Add support for variants to DW HDMI PHYJernej Skrabec
There are multiple variants of DW HDMI PHYs in Allwinner SoCs. While some things like clock and reset setup are the same, PHY configuration differs a lot. Split out code which is PHY specific to separate functions and create a structure which holds pointers to those functions. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-11-jernej.skrabec@siol.net
2018-03-02drm/sun4i: Fix polarity configuration for DW HDMI PHYJernej Skrabec
Current polarity configuration code is cleary wrong since it compares same flag two times. However, even if flag name is fixed, it won't work well for resolutions which have one polarity positive and another negative. Fix that by properly set each bit according to each polarity. Since those two bits are not described in any documentation, relationships were obtained by experimentation. Fixes: b7c7436a5ff0 ("drm/sun4i: Implement A83T HDMI driver") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-10-jernej.skrabec@siol.net
2018-02-16drm/sun4i: Implement A83T HDMI driverJernej Skrabec
A83T has DW HDMI IP block with a custom PHY similar to Synopsys gen2 HDMI PHY. Only video output was tested, while HW also supports audio and CEC. Support for them will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180214200906.31509-11-jernej.skrabec@siol.net
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