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authorJunhui Liu <junhui.liu@pigmoral.tech>2025-10-21 17:41:45 +0800
committerConor Dooley <conor.dooley@microchip.com>2025-11-12 17:06:56 +0000
commit9c96219602b1a29c1959c5799aa3e6c5e14e395c (patch)
tree6da154a2b768e8b778727f07a332348a3d81aa78
parenta94f9be29464f85e97683901162ca236dde40dc7 (diff)
riscv: Add Anlogic SoC famly Kconfig support
The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-rw-r--r--arch/riscv/Kconfig.socs5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 848e7149e443..25f7e58cbf74 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config ARCH_ANDES
help
This enables support for Andes SoC platform hardware.
+config ARCH_ANLOGIC
+ bool "Anlogic SoCs"
+ help
+ This enables support for Anlogic SoC platform hardware.
+
config ARCH_ESWIN
bool "ESWIN SoCs"
help