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2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2023-05-31ARM: dts: meson8: correct uart_B and uart_C clock referencesMartin Blumenstingl
On Meson8 uart_B and uart_C do not work, because they are relying on incorrect clocks. Change the references of pclk to the correct CLKID (UART1 for uart_B and UART2 for uart_C), to allow use of the two uarts. This was originally reported by Hans-Frieder Vogt for Meson8b [0], but the same bug is also present in meson8.dtsi [0] https://lore.kernel.org/linux-amlogic/trinity-bf20bcb9-790b-4ab9-99e3-0831ef8257f4-1680878185420@3c-app-gmx-bap55/ Fixes: 57007bfb5469 ("ARM: dts: meson8: Fix the UART device-tree schema validation") Reported-by: Hans-Frieder Vogt <hfdevel@gmx.net> # for meson8b.dtsi Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230516203029.1031174-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-03-22ARM: dts: meson8: add the SDXC_A pinsMartin Blumenstingl
Add the pins for the SDHC MMC controller which connect to the SDIO wifi on some boards. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230321171213.2808460-3-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-03-22ARM: dts: meson8: add the xtal_32k_out pinMartin Blumenstingl
GPIOX_10 can generate a 32768Hz signal when enabling the "xtal_32k_out" group with the xtal function. This is typically used as LPO clock for the SDIO wifi chips. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230321171213.2808460-2-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20ARM: dts: meson8: align OPP table names with DT schemaKrzysztof Kozlowski
DT schema expects names of operating points tables to match certain pattern: meson8-minix-neo-x8.dtb: gpu-opp-table: $nodename:0: 'gpu-opp-table' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230120072108.138598-1-krzysztof.kozlowski@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-19ARM: dts: meson8: Add more L2 (PL310) cache propertiesMartin Blumenstingl
Add more L2 cache properties which are used by the 3.10 vendor kernel but have not made it upstream yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230114233455.2005047-2-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-06-10ARM: dts: meson: adjust whitespace around '='Krzysztof Kozlowski
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220526204552.832961-2-krzysztof.kozlowski@linaro.org
2022-01-10ARM: dts: meson8: Fix the UART device-tree schema validationMartin Blumenstingl
The dt-bindings for the UART controller only allow the following values for Meson8 SoCs: - "amlogic,meson8-uart", "amlogic,meson-ao-uart" - "amlogic,meson8-uart" Use the correct fallback compatible string "amlogic,meson-ao-uart" for AO UART. Drop the "amlogic,meson-uart" compatible string from the EE domain UART controllers. Also update the order of the clocks to match the order defined in the yaml schema. Fixes: 6ca77502050eff ("ARM: dts: meson8: use stable UART bindings with correct gate clock") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20211227180026.4068352-3-martin.blumenstingl@googlemail.com
2021-07-26ARM: dts: meson: Add the AIU audio controllerMartin Blumenstingl
Add the AIU audio controller to the Amlogic Meson6/8/8b/8m2 SoC DT. This provides I2S and SPDIF outputs as well as codec glues for the internal HDMI controller. Also add the clock inputs and pin mux definitions on Meson8/8b/8m2. On Meson6 this is omitted because we neither have a clock nor pin controller node there yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210717233030.331273-2-martin.blumenstingl@googlemail.com
2021-07-26ARM: dts: meson8: Use a higher default GPU clock frequencyMartin Blumenstingl
We are seeing "imprecise external abort (0x1406)" errors during boot (which then cause the whole board to hang) on Meson8 (but not Meson8m2). These are observed while trying to access the GPU's registers when the MALI clock is running at it's default setting of 24MHz. The 3.10 vendor kernel uses 318.75MHz as "default" GPU frequency. Using that makes the "imprecise external aborts" go away. Add the assigned-clocks and assigned-clock-rates properties to also bump the MALI clock to 318.75MHz before accessing any of it's registers. Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Reported-by: Demetris Ierokipides <ierokipides.dem@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210711214023.2163565-1-martin.blumenstingl@googlemail.com
2021-02-09Merge tag 'amlogic-dt64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: amlogic updates for v5.12 - new board: Hardkernel ODROID-HC4 (SoC: SM1) - new board: Beelink GS-King-X (SoC: S922X) - shorten shorten audio card names for alsa compatibility - misc cleanups & fixes * tag 'amlogic-dt64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson: add initial device-tree for ODROID-HC4 dt-bindings: arm: amlogic: add ODROID-HC4 bindings arm64: dts: meson: convert meson-sm1-odroid-c4 to dtsi arm64: dts: meson: sort Amlogic dtb Makefile dt-bindings: arm: amlogic: sort SM1 bindings arm64: dts: meson: fix broken wifi node for Khadas VIM3L arm64: dts: meson: add i2c3/rtc nodes and rtc aliases to ODROID-N2 dtsi ARM: dts: meson: add the AO ARC remote processor dt-bindings: Amlogic: add the documentation for the SECBUS2 registers dt-bindings: sram: Add compatible strings for the Meson AO ARC SRAM arm64: dts: meson: shorten audio card names for alsa compatibility arm64: dts: meson: add initial Beelink GS-King-X device-tree dt-bindings: arm: amlogic: add support for the Beelink GS-King-X arm64: dts: meson: Fix schema warnings for pwm-leds arm64: dts: meson: vim3: whitespace fixups arm64: dts: meson: switch TFLASH_VDD_EN pin to open drain on Odroid-C4 Revert "arm64: dts: amlogic: add missing ethernet reset ID" arm64: dts: amlogic: meson-g12: Set FL-adj property value Link: https://lore.kernel.org/soc/7heehq7ag3.fsf@baylibre.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-03ARM: dts: meson: add the AO ARC remote processorMartin Blumenstingl
The 32-bit Amlogic Meson SoCs embed an ARC processor in the Always-On power domain which is typically used for managing system suspend. The memory for this ARC core is taken from the AHB SRAM area. Depending on the actual SoC a different ARC core is used: - Meson6 and earlier: some ARCv1 ISA based core (probably an ARC625) - Meson8 and later: an ARC EM4 (ARCv2 ISA) based core Add the device-tree node for this remote-processor along with the required SRAM sections, clocks and reset-lines. Also use the SoC-specific compatible string to manage any differences (should they exist). On Meson8, Meson8b and Meson8m2 the "secbus2" IO region is needed as some bits need to be programmed there. Add this IO region for those SoCs as well. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20210102205904.2691120-6-martin.blumenstingl@googlemail.com
2021-01-25ARM: dts: meson8: add the thermal-zones with cooling configurationMartin Blumenstingl
The vendor kernel uses the following thermal-zone settings: <= 70°C: - CPU frequency limited to 1.608GHz - GPU limited to 511MHz and 5 cores (pixel processors) <= 80°C: - CPU frequency limited to 1.2GHz - GPU limited to 435MHz and 4 cores (pixel processors) <= 90°C: - CPU frequency limited to 0.804GHz - GPU limited to 328MHz and 3 cores (pixel processors) Add simplified thermal configuration which is taken from the GXBB/GXL/GXM SoC family (which uses the same manufacturing process and has the same maximum junction temperature of 125°C). With this the thermal framework will try to keep the SoC temperature at or below 80°C which is identical to the vendor kernel (with the exception of one GPU pixel processor). The number of GPU cores are not taken into account as this is not supported. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201221181306.904272-4-martin.blumenstingl@googlemail.com
2020-10-02ARM: dts: meson8: remove two invalid interrupt lines from the GPU nodeMartin Blumenstingl
The 3.10 vendor kernel defines the following GPU 20 interrupt lines: #define INT_MALI_GP AM_IRQ(160) #define INT_MALI_GP_MMU AM_IRQ(161) #define INT_MALI_PP AM_IRQ(162) #define INT_MALI_PMU AM_IRQ(163) #define INT_MALI_PP0 AM_IRQ(164) #define INT_MALI_PP0_MMU AM_IRQ(165) #define INT_MALI_PP1 AM_IRQ(166) #define INT_MALI_PP1_MMU AM_IRQ(167) #define INT_MALI_PP2 AM_IRQ(168) #define INT_MALI_PP2_MMU AM_IRQ(169) #define INT_MALI_PP3 AM_IRQ(170) #define INT_MALI_PP3_MMU AM_IRQ(171) #define INT_MALI_PP4 AM_IRQ(172) #define INT_MALI_PP4_MMU AM_IRQ(173) #define INT_MALI_PP5 AM_IRQ(174) #define INT_MALI_PP5_MMU AM_IRQ(175) #define INT_MALI_PP6 AM_IRQ(176) #define INT_MALI_PP6_MMU AM_IRQ(177) #define INT_MALI_PP7 AM_IRQ(178) #define INT_MALI_PP7_MMU AM_IRQ(179) However, the driver from the 3.10 vendor kernel does not use the following four interrupt lines: - INT_MALI_PP3 - INT_MALI_PP3_MMU - INT_MALI_PP7 - INT_MALI_PP7_MMU Drop the "pp3" and "ppmmu3" interrupt lines. This is also important because there is no matching entry in interrupt-names for it (meaning the "pp2" interrupt is actually assigned to the "pp3" interrupt line). Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Reported-by: Thomas Graichen <thomas.graichen@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: thomas graichen <thomas.graichen@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200815181957.408649-1-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson: add the SDHC MMC controllerMartin Blumenstingl
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller IP which typically connects to an eMMC chip (because unlike the SDIO controller the SDHC controller has an 8-bit bus interface). On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. However, Meson8m2 seems to have an improved version of the SHDC controller IP which doesn't require the driver to wait manually for a flush of a DMA transfer. Thus every SoC has it's own compatible string so if more difference are discovered they can be implemented. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson8: add power domain controllerMartin Blumenstingl
The Meson8 SoCs have a power domain controller which can turn on/off various register areas (such as: Ethernet, VPU, etc.). Add the main "pwrc" controller and configure the Ethernet power domain. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620161010.23171-2-martin.blumenstingl@googlemail.com
2020-02-08Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM Device-tree updates from Olof Johansson: "New SoCs: - Atmel/Microchip SAM9X60 (ARM926 SoC) - OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants of it with different GPU/media IP configurations. - ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU) - ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500) - Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem) - Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class) New boards: - Allwinner: + Emlid Neutis SoM (H3 variant) + Libre Computer ALL-H3-IT + PineH64 Model B - Amlogic: + Libretech Amlogic GX PC (s905d and s912-based variants) - Atmel/Microchip: + Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1) - Marvell: + Armada 385-based SolidRun Clearfog GTR - NXP: + Gateworks GW59xx boards based on i.MX6/6Q/6QDL + Tolino Shine 3 eBook reader (i.MX6sl) + Embedded Artists COM (i.MX7ULP) + SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems) + Google Coral Edge TPU (i.MX8MQ) - Rockchip: + Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs) + Radxa Rock Pi N10 (RK3399Pro-based) + VMARC RK3399Pro SOM - ST: + Reference boards for stm32mp15 - ST Ericsson: + Samsung Galaxy S III mini (GT-I8190) + HREF520 reference board for DB8520 - TI OMAP: + Gen1 Amazon Echo (OMAP3630-based) - Qualcomm: + Inforce 6640 Single Board Computer (msm8996-based) + SC7180 IDP (SC7180-based)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits) dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera arm64: dts: ti: k3-am65-main Add CAL node arm64: dts: ti: k3-j721e-main: Add McASP nodes arm64: dts: ti: k3-am654-main: Add McASP nodes arm64: dts: ti: k3-j721e: DMA support arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS arm64: dts: ti: k3-am65: DMA support arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss arm64: dts: ti: k3-am65-main: Correct main NAVSS representation ARM: dts: aspeed: rainier: Add UCD90320 power sequencer ARM: dts: aspeed: rainier: Switch PSUs to unknown version arm64: dts: rockchip: Kill off "simple-panel" compatibles ARM: dts: rockchip: Kill off "simple-panel" compatibles arm64: dts: rockchip: rename dwmmc node names to mmc ARM: dts: rockchip: rename dwmmc node names to mmc arm64: dts: exynos: Rename Samsung and Exynos to lowercase arm64: dts: uniphier: add reset-names to NAND controller node ...
2020-01-08ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPPMartin Blumenstingl
The clock setup on Meson8 cannot achieve a Mali frequency of exactly 182.15MHz. The vendor driver uses "FCLK_DIV7 / 2" for this frequency, which translates to 2550MHz / 7 / 2 = 182142857Hz. Update the GPU operating point to that specific frequency to not confuse myself when comparing the frequency from the .dts with the actual clock rate on the system. Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-11ARM: dts: meson8: add the DDR clock controllerMartin Blumenstingl
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-11ARM: dts: meson: provide the XTAL clock using a fixed-clockMartin Blumenstingl
The clock controller driver has provided the XTAL clock so far. This does not match how the hardware actually works because the XTAL clock is an actual crystal which is mounted on the PCB. Add the "xtal" clock to meson.dtsi and replace all references to the clock controller's CLKID_XTAL with the new xtal clock node. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09ARM: dts: meson8: fix the size of the PMU registersMartin Blumenstingl
The PMU registers are at least 0x18 bytes wide. Meson8b already uses a size of 0x18. The structure of the PMU registers on Meson8 and Meson8b is similar but not identical. Meson8 and Meson8b have the following registers in common (starting at AOBUS + 0xe0): #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) Meson8b additionally has these three registers: #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) Thus we can assume that the register size of the PMU IP blocks is identical on both SoCs (and Meson8 just contains some reserved registers in that area) because the CEC registers start right after the PMU (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). The upcoming power domain driver will need to read and write the AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated size is needed for that driver to work. Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-07-19Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM Devicetree updates from Olof Johansson: "We continue to see a lot of new material. I've highlighted some of it below, but there's been more beyond that as well. One of the sweeping changes is that many boards have seen their ARM Mali GPU devices added to device trees, since the DRM drivers have now been merged. So, with the caveat that I have surely missed several great contributions, here's a collection of the material this time around: New SoCs: - Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53) - TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA) - Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53) New Boards / platforms: - Aspeed BMC support for a number of new server platforms - Kontron SMARC SoM (several i.MX6 versions) - Novtech's Meerkat96 (i.MX7) - ST Micro Avenger96 board - Hardkernel ODROID-N2 (Amlogic G12B) - Purism Librem5 devkit (i.MX8MQ) - Google Cheza (Qualcomm SDM845) - Qualcomm Dragonboard 845c (Qualcomm SDM845) - Hugsun X99 TV Box (Rockchip RK3399) - Khadas Edge/Edge-V/Captain (Rockchip RK3399) Updated / expanded boards and platforms: - Renesas r7s9210 has a lot of new peripherals added - Fixes and polish for Rockchip-based Chromebooks - Amlogic G12A has a lot of peripherals added - Nvidia Jetson Nano sees various fixes and improvements, and is now at feature parity with TX1" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (586 commits) ARM: dts: gemini: Set DIR-685 SPI CS as active low ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family ARM: dts: exynos: Move Mali400 GPU node to "/soc" ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210 arm64: dts: qcom: qcs404: Add missing space for cooling-cells property arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs arm64: dts: rockchip: enable rk3328 watchdog clock ARM: dts: rockchip: add display nodes for rk322x ARM: dts: rockchip: fix vop iommu-cells on rk322x arm64: dts: rockchip: Add support for Hugsun X99 TV Box arm64: dts: rockchip: Define values for the IPA governor for rock960 arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance. Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie" ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron arm64: dts: qcom: sdm845-cheza: add initial cheza dt ARM: dts: msm8974-FP2: Add vibration motor ...
2019-06-03ARM: dts: meson8: update with SPDX Licence identifierNeil Armstrong
While the text specifies "of the GPL or the X11 license" the actual license text matches the MIT license as specified at [0] [0] https://spdx.org/licenses/MIT.html Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-05-22ARM: dts: meson8: add the canvas moduleMartin Blumenstingl
Add the canvas module to Meson8 because it's required for the VPU (video output) and video decoders. The canvas module is located inside thie "DMC bus" (where also some of the memory controller registers are located). The "DMC bus" itself is part of the so-called "MMC bus". Amlogic's vendor kernel has an explicit #define for the "DMC" register range on Meson8m2 while there's no such #define for Meson8. However, the canvas and memory controller registers on Meson8 are all expressed as "0x6000 + actual offset", while Meson8m2 uses "DMC + actual offset". Thus it's safe to assume that the DMC bus exists on both SoCs even though the registers inside are slightly different. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-05-20ARM: dts: meson8: fix GPU interrupts and drop an undocumented propertyMartin Blumenstingl
The interrupts in Amlogic's vendor kernel sources are all contiguous. There are two typos leading to pp2 and pp4 as well as ppmmu2 and ppmmu4 incorrectly sharing the same interrupt line. Fix this by using interrupt 170 for pp2 and 171 for ppmmu2. Also drop the undocumented "switch-delay" which is a left-over from my experiments with an early lima kernel driver when it was still out-of-tree and required this property on Amlogic SoCs. Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16ARM: dts: meson: add support for the RTCMartin Blumenstingl
The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The RTC requires an external 32.768 kHz oscillator to work properly. Whether or not this crystal exists depends on the board, so it has to be added for each board.dts (instead of adding it somewhere in a generic .dtsi). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18ARM: dts: meson8: add the internal clock measurerMartin Blumenstingl
The Amlogic Meson8 SoC has an internal clock measurer IP which allows measuring frequencies of various clock paths. Enable it on meson8.dtsi so we can use it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11ARM: dts: meson8: add the temperature calibration data for the SAR ADCMartin Blumenstingl
The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11ARM: dts: meson: switch the clock controller to the HHI register areaMartin Blumenstingl
The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-10ARM: dts: meson8: add the Mali-450 MP6 GPUMartin Blumenstingl
Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the latter inherits meson8.dtsi). These SoCs have a Mali-450 GPU with six pixel processors. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV7 | 1, /* 182.1 Mhz */ FCLK_DEV4 | 1, /* 318.7 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-10ARM: dts: meson8: add the APB busMartin Blumenstingl
Various peripherals (Mali GPU, NAND controller, VPU, etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson: meson8: add the CPU OPP tableMartin Blumenstingl
The values are taken from Amlogic's 3.10 kernel sources. Their sources have a "meson8m2_n200_2G.dtd" which defines a different voltage table: - 0.86V for 96MHz - (values in between omitted) - 1.14V for 1.992GHz The reason for this is simply the hardware design because the voltage regulator on this board is has a minimum output of 0.86V and a maximum output of 1.14V. The recommended settings are added with this patch instead of using the values that are only valid for one board. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson8: add the Cortex-A9 global timerMartin Blumenstingl
The Meson8 and Meson8m2 SoCs are using four Cortex-A9 cores. These come with an ARM global timer. This adds the Cortex-A9 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson8: add the ARM TWD timerMartin Blumenstingl
The Meson8 and Meson8m2 SoC are using four ARM Cortex-A9 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on these two SoCs. Suggested-by: Carlo Caione <carlo@endlessm.com> [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripheralsMartin Blumenstingl
The public Meson8b (S805) datasheet describes a memory region called "A9 Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a simple-bus node and move all peripherals that are part of this memory region. This makes the .dts a bit easier to read. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-28ARM: dts: meson: add the clock inputs for the Meson timerMartin Blumenstingl
The Meson Timer IP block has two clock inputs: - clk81 for using the system clock as timebase - xtal for a timebase with 1us, 10us, 100us and 1ms resolution The clocksource driver does not use these yet, but it's still a good idea to add them as this describes how the hardware actually works internally. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-28ARM: dts: meson: consistently disable pin biasJerome Brunet
On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies. As we have seen with the eMMC, depending on the bias type and the function, it may trigger problems. The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we will get is undefined. There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option. This change consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-04ARM: dts: meson8: fix the clock controller register sizeMartin Blumenstingl
The clock controller registers are not 0x460 wide because the reset controller starts at CBUS 0x4404. This currently overlaps with the clock controller (which is at CBUS 0x4000). There is no public documentation available on the actual size of the clock controller's register area (also called "HHI"). However, in Amlogic's GPL kernel sources the last "HHI" register is HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size doesn't seem unlikely. Fixes: 2c323c43a3d619 ("ARM: dts: meson8: add and use the real clock controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-05-10ARM: dts: meson8: add the uart_A pinsMartin Blumenstingl
This adds the pins for uart_A, which is used to connect to the Bluetooth module on some devices. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-04-27ARM: dts: meson8: add the cortex-a9-pmu compatible PMUMartin Blumenstingl
Enable the performance monitor unit on Meson8. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-02-12ARM: dts: meson8: add the USB reset lineMartin Blumenstingl
Now that we support the reset controller on Meson8 we can add the reset line to the USB PHYs (just like on Meson8b). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-02-12ARM: dts: meson8: add the reset controllerMartin Blumenstingl
Meson8 uses the same reset controller as Meson8b. Add the node along with the #include for the reset lines to meson8.dtsi so we can use it from there as well. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-11ARM: dts: meson8: enable the GPIO interrupt controllerMartin Blumenstingl
This enables the GPIO interrupt controller for the Meson8 SoCs. Interrupt support on the GPIOs can be used by the MMC framework to detect when an SD card is inserted/removed or by the input framework to detect button presses. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-06ARM: dts: meson8: use stable UART bindings with correct gate clockMartin Blumenstingl
Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-06ARM: dts: meson: drop "sana" clock from SAR ADCXingyu Chen
The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-06ARM: dts: meson8: add more L2 cache settingsMartin Blumenstingl
Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 4096 sets, CACHE_ID 0x4100a0c9, Cache size: 1048576 B AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Two differences still remain: - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-30Merge tag 'amlogic-dt64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Pull "Amlogic 64-bit platforms: DT updates for v4.15" from Kevin Hilman: - new SoC support: A113D - new boards: Tronsmart Vega S96, Khadas vim2 - reserved memory fixups - gpio-names cleanups - MMC cleanups, enable high-speed modes - misc cleanups * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-axg: add initial A113D SoC DT support dt-bindings: arm: amlogic: Add Meson AXG binding ARM64: dts: meson-gx: remove unnecessary uart compatible ARM64: dts: meson-gx: remove unnecessary clocks properties ARM64: dts: meson-gxl: Add alternate ARM Trusted Firmware reserved memory zone ARM64: dts: meson-gxm: enable HS400 on the vim2 ARM64: dts: meson-gxbb-nexbox-a95x: Enable USB Nodes dt-bindings: arm: amlogic: Add Tronsmart Vega S96 binding ARM64: dts: meson-gxm: Add Vega S96 board ARM64: dts: meson-gxm: Add support for Khadas VIM2 ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins ARM64: dts: meson-gxl: adjust libretech-cc gpio-line-names ARM64: dts: meson-gxl: adjust kvim gpio-line-names ARM64: dts: meson-gxbb: adjust odroid-c2 gpio-line-names ARM64: dts: meson-gxbb: adjust nanopi-k2 gpio-line-names ARM64: dts: meson-gx: adjust gpio-ranges for TEST_N ARM64: dts: meson-gx: remove gpio offset ARM: dts: meson8: remove gpio offset ARM64: dts: meson-gxl-libretech-cc: enable internal phy leds ARM64: dts: meson-gxl-libretech-cc: enable saradc
2017-10-29ARM: dts: meson: add the efuse nodeMartin Blumenstingl
Meson6, Meson8 and Meson8b use a similar IP block which has access to 512 bytes of efuse data. During SoC manufacturing some calibration settings for the CVBS connector and the internal temperature sensor are written to this efuse. On some boards it additionally stores for example the MAC addresses. The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6 since we do not have a clock driver there (which is required to read data from the efuse). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-29ARM: dts: meson8: add support for booting the secondary CPU coresMartin Blumenstingl
Booting the secondary CPU cores involves the following nodes/devices: - SCU (Snoop-Control-Unit, for which we already have a DT node) - a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller - the PMU (power management unit) which controls the power of the CPU cores - a range in the SRAM specifically reserved for booting secondary CPU cores - the "enable-method" which activates booting the secondary CPU cores This adds all required nodes and properties to boot the secondary CPU cores. Suggested-by: Carlo Caione <carlo@caione.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-11ARM: dts: meson: add the SDIO MMC controllerMartin Blumenstingl
Meson6, Meson8 and Meson8b are using the same MMC controller IP. This adds the MMC controller node to meson.dtsi so it can be used by all SoCs. The controller itself is a bit special, because it has multiple slots. Each slot is accessed through a sub-node of the controller. However, currently the driver for this hardware only supports one slot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit (git 2.34.1) at 2024-05-22 09:59:38 +0000