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2025-03-14Merge tag 'tegra-for-6.15-arm64-dt-v2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.15-rc1 This contains a patch to remove an unusable key that was erroneously exposed as well as a fix to support GPUs with a large amount of video memory on IGX Orin. Finally, some additional devices, such as a temperature sensor, are enabled on Jetson TX1, the output voltage of some pins is adjusted and the VDD_LCD_1V8_DIS power supply now uses the correct enable GPIO. * tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: p2180: Add TMP451 temperature sensor node arm64: tegra: p2597: Enable TCA9539 as IRQ controllers arm64: tegra: Define pinmuxing for gpio pads on Tegra210 arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator arm64: tegra: Resize aperture for the IGX PCIe C5 slot arm64: tegra: Remove the Orin NX/Nano suspend key Link: https://lore.kernel.org/r/20250307174938.3456275-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-03-07arm64: tegra: p2180: Add TMP451 temperature sensor nodeDiogo Ivo
The Jetson TX1 module contains a TI TMP451 temperature sensor. Add a DT node for it. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-4-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: p2597: Enable TCA9539 as IRQ controllersDiogo Ivo
Fill out the DT nodes enabling both TCA9539 chips as IRQ controllers. Proper functionality was tested for both instances. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-3-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: Define pinmuxing for gpio pads on Tegra210Diogo Ivo
As the gpio pads are capable of operating at either 1.8V or 3.3V add both options to the pinmuxing so that the appropriate level can be set depending on the voltage of the regulator driving the pads. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-2-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulatorDiogo Ivo
According to the board schematics the enable pin of this regulator is connected to gpio line #9 of the first instance of the TCA9539 GPIO expander, so adjust it. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20250224-diogo-gpio_exp-v1-1-80fb84ac48c6@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: Resize aperture for the IGX PCIe C5 slotJon Hunter
Some discrete graphics cards such as the NVIDIA RTX A6000 support resizable BARs. When connecting an A6000 card to the NVIDIA IGX Orin platform, resizing the BAR1 aperture to 8GB fails because the current device-tree configuration for the PCIe C5 slot cannot support this. Fix this by updating the device-tree 'reg' and 'ranges' properties for the PCIe C5 slot to support this. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20250116151903.476047-1-jonathanh@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-07arm64: tegra: Remove the Orin NX/Nano suspend keyNinad Malwade
As per the Orin Nano Dev Kit schematic, GPIO_G.02 is not available on this device family. It should not be used at all on Orin NX/Nano. Having this unused pin mapped as the suspend key can lead to unpredictable behavior for low power modes. Orin NX/Nano uses GPIO_EE.04 as both a "power" button and a "suspend" button. However, we cannot have two gpio-keys mapped to the same GPIO. Therefore remove the "suspend" key. Cc: stable@vger.kernel.org Fixes: e63472eda5ea ("arm64: tegra: Support Jetson Orin NX reference platform") Signed-off-by: Ninad Malwade <nmalwade@nvidia.com> Signed-off-by: Ivy Huang <yijuh@nvidia.com> Link: https://lore.kernel.org/r/20250206224034.3691397-1-yijuh@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-03-06arm64: dts: nvidia: Remove unused and undocumented ↵Rob Herring (Arm)
"regulator-ramp-delay-scale" property Remove "regulator-ramp-delay-scale" property which is both unused in the kernel and undocumented. Most likely they are leftovers from downstream. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250305224952.2995841-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-10arm64: tegra: Fix Tegra234 PCIe interrupt-mapBrad Griffis
For interrupt-map entries, the DTS specification requires that #address-cells is defined for both the child node and the interrupt parent. For the PCIe interrupt-map entries, the parent node ("gic") has not specified #address-cells. The existing layout of the PCIe interrupt-map entries indicates that it assumes that #address-cells is zero for this node. Explicitly set #address-cells to zero for "gic" so that it complies with the device tree specification. NVIDIA EDK2 works around this issue by assuming #address-cells is zero in this scenario, but that workaround is being removed and so this update is needed or else NVIDIA EDK2 cannot successfully parse the device tree and the board cannot boot. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20241213235602.452303-1-bgriffis@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-01-09arm64: tegra: Disable Tegra234 sce-fabric nodeSumit Gupta
Access to safety cluster engine (SCE) fabric registers was blocked by firewall after the introduction of Functional Safety Island in Tegra234. After that, any access by software to SCE registers is correctly resulting in the internal bus error. However, when CPUs try accessing the SCE-fabric registers to print error info, another firewall error occurs as the fabric registers are also firewall protected. This results in a second error to be printed. Disable the SCE fabric node to avoid printing the misleading error. The first error info will be printed by the interrupt from the fabric causing the actual access. Cc: stable@vger.kernel.org Fixes: 302e154000ec ("arm64: tegra: Add node for CBB 2.0 on Tegra234") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Ivy Huang <yijuh@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20241218000737.1789569-3-yijuh@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-01-09arm64: tegra: Fix typo in Tegra234 dce-fabric compatibleSumit Gupta
The compatible string for the Tegra DCE fabric is currently defined as 'nvidia,tegra234-sce-fabric' but this is incorrect because this is the compatible string for SCE fabric. Update the compatible for the DCE fabric to correct the compatible string. This compatible needs to be correct in order for the interconnect to catch things such as improper data accesses. Cc: stable@vger.kernel.org Fixes: 302e154000ec ("arm64: tegra: Add node for CBB 2.0 on Tegra234") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Ivy Huang <yijuh@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20241218000737.1789569-2-yijuh@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-01-09arm64: tegra: Fix DMA ID for SPI2Akhil R
DMA ID for SPI2 is '16'. Update the incorrect value in the devicetree. Fixes: bb9667d8187b ("arm64: tegra: Add SPI device tree nodes for Tegra234") Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Link: https://lore.kernel.org/r/20241206105201.53596-1-akhilrajeev@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-10-24arm64: tegra: smaug: Declare cros-ec extconDiogo Ivo
Leverage the Chrome OS EC in the Pixel C to convey information about the state of the USB-C port via the extcon class. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Link: https://lore.kernel.org/r/20241001-cros_ec_extcon-v1-1-1e212a1a4bbc@tecnico.ulisboa.pt Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-10-24arm64: tegra: Add SDMMC sdr104-offsets for Tegra X1Diogo Ivo
Define the sdr104-specific offsets, preventing the driver from defaulting to the 1.8V offsets, which cause the system to hang during the SDR104 mode calibration. The zeroing of these values was chosen since it restores functionality and no better suggestions are provided by the Tegra X1 TRM. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-10-24arm64: dts: nvidia: tegra210-smaug: Add TMP451 temperature sensor nodeJasper Korten
The Google Pixel C contains a TI TMP451 temperature sensor. Add a DT node for temperature sensor. Information gathered from downstream tree. Link: https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo-m8/arch/arm64/boot/dts/tegra/tegra210-smaug.dtsi#1000 Signed-off-by: Jasper Korten <jja2000@gmail.com> Tested-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-10-24arm64: dts: nvidia: tegra210-smaug: Add touchscreen nodeJasper Korten
The Google Pixel C contains a RMI4 HID over I2C touchscreen. Add a DT node for the touchscreen. Information gathered from downstream tree. Link: https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo-m8/arch/arm64/boot/dts/tegra/tegra210-smaug.dtsi#542 Signed-off-by: Jasper Korten <jja2000@gmail.com> Tested-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-10-24arm64: tegra: p2180: Add mandatory compatible for WiFi nodeTomasz Maciej Nowak
The dtschema requires to specify common ancestor which all SDIO chips are derived from, so add accordingly. Fixes: a50d5dcd2815 ("arm64: tegra: Wire up WiFi on Jetson TX1 module") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409030438.8tumAnp1-lkp@intel.com Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-10-21arm64: tegra: Create SKU8 AGX Orin board fileDara Stotland
The existing tegra234-p3737-0000+p3701-0000.dtb is compatible with the following modules: p3701-0000 p3701-0004 p3701-0005 Add support for p3701-0008. Move data that is common to all SKUs to a new file called tegra234-p3737-0000+p3701.dtsi. Update Makefile. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Add thermal nodes to AGX Orin SKU8Dara Stotland
One of the key differences between p3701-0000 and p3701-0008 is the temperature range. Add this info for p3701-0008. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Move BPMP nodes to AGX Orin moduleDara Stotland
All SKUs of the p3701 module contain a temp sensor connected to the BPMP I2C. Move the associated nodes from tegra234-p3701-0008.dtsi to tegra234-p3701.dtsi. Add missing compatible. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Move padctl supply nodes to AGX Orin moduleDara Stotland
Some padctl supply nodes currently reside in board file, when they should reside on module level. The nodes are part of module, not board. Move these nodes to the correct AGX Orin module file. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Move AGX Orin nodes to correct locationDara Stotland
Some of the nodes inside the AGX Orin module file are in the wrong location. In particular, the SD card interface and two of the PCIe regulators in the module file should instead reside in the board file. These components are not part of the module. They are part of the carrier board. Move these nodes to the correct location. Fixes: cd42b26a527f ("arm64: tegra: Add regulators required for PCIe") Fixes: d71b893a119d ("arm64: tegra: Add Tegra234 SDMMC1 device tree node") Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Combine IGX Orin board filesDara Stotland
Current IGX Orin structure has both a top-level module+board file as well as a board file. Most of the data in the board-file is closely related to the module itself. The benefit of this extra file is outweighed by the additional complexity. Merge the board file into the module+board file for simplicity. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Combine AGX Orin board filesDara Stotland
The current AGX Orin structure has both a top-level module+board file as well as a board file. Most of the data in the board-file is closely related to the module itself. The benefit of this extra file is outweighed by the additional complexity. Merge the board file into the module+board file for simplicity. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Add common nodes to AGX Orin moduleDara Stotland
The AGX Orin module boards contain common nodes that can be moved to the included module dtsi. This eliminates redundancy within the files and reduces lines of code. Data from tegra234-p3701-0000 and tegra234-p3701-0008 that is common is now in tegra234-p3701.dtsi. Signed-off-by: Dara Stotland <dstotland@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Wire up WiFi on Jetson TX1 moduleTomasz Maciej Nowak
P2180 modules have WiFi in form of BCM4354 chip, and kernel driver supports this one, so enable it for all users. The necessary calibration file can be obtained from Jetson Linux Archive. nvram.txt file is located in "Driver Package (BSP)" in nv_tegra/l4t_deb_packages/nvidia-l4t-firmware_<version>_arm64.deb archive. The rest of necessary blobs can be obtained from official Linux Firmware repository or (newer ones) from Infineon ifx-linux-firmware repository (look in older releases). Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Wire up Bluetooth on Jetson TX1 moduleTomasz Maciej Nowak
P2180 modules have Bluetooth in form of BCM4354 chip, and kernel driver supports this one, so enable it for all users. The necessary firmware can be obtained from Jetson Linux Archive. bcm4354.hcd file is located in "Driver Package (BSP)" in nv_tegra/l4t_deb_packages/nvidia-l4t-firmware_<version>_arm64.deb archive. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Wire up power sensors on Jetson TX1 DevKitTomasz Maciej Nowak
One INA3221 sensor is located on P2180 module and the other two are on P2597 base board. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Add p3767 PCIe C4 EP detailsVedant Deshpande
Add implementation details for Orin NX/Nano PCIe EP on C4. Signed-off-by: Vedant Deshpande <vedantd@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Add Tegra234 PCIe C4 EP definitionVedant Deshpande
Add PCIe C4 EP controller definition in device tree for Tegra234 devices. Signed-off-by: Vedant Deshpande <vedantd@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Add wp-gpio for P2597's external card slotDiogo Ivo
Add the definition for the wp-gpio of the P2597's external card slot, enabling this functionality. Tested on a P2597 board. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-29arm64: tegra: Fix gpio for P2597 vmmc regulatorDiogo Ivo
The current declaration is off-by-one and actually corresponds to the wp-gpio of the external slot. Tested on a P2597 board. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-27arm64: tegra: Correct location of power-sensors for IGX OrinJon Hunter
The power-sensors are located on the carrier board and not the module board and so update the IGX Orin device-tree files to fix this. Fixes: 9152ed09309d ("arm64: tegra: Add power-sensors for Tegra234 boards") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-27arm64: tegra: enable same UARTs for Orin NX/NanoVedant Deshpande
This patch ensures that Orin NX and Orin Nano enable an identical set of serial ports. UARTA/UARTE will be enabled by adding respective nodes to the board dtsi file. Signed-off-by: Vedant Deshpande <vedantd@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-27arm64: tegra: Add DMA properties for Tegra234 UARTAVedant Deshpande
Adding the missing dmas and dma-names properties which are required for UARTA when using with the Tegra HSUART driver. Signed-off-by: Vedant Deshpande <vedantd@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-06-28arm64: tegra: Restructure Orin NX/Nano device treeVedant Deshpande
The Orin NX and Orin Nano boards share a common carrier board and the module boards for both platforms are very similar. Therefore, restructure the Orin NX/Nano device-tree source files to adhere to a simple hierarchical format. This will help make clear where changes should go, and eliminates redundancy within the files. Previously the carrier board file was independent. However, given that it is so tightly coupled with the module design, it will be more practical to combine files together for a simpler layout. Following changes are made to restructure the device tree source files: 1) Change include hierarchy. Top-level dts includes board dtsi. Board dtsi includes module dtsi. Module dtsi includes SoC dtsi. 2) Data from the top level dts file that is common to both Orin NX and Orin Nano is in tegra234-p3768-0000+p3767.dtsi. 3) Only data that is unique to NX/Nano is present in the top-level dts. Signed-off-by: Vedant Deshpande <vedantd@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-05-02arm64: dts: Add/fix /memory node unit-addressesRob Herring
'/memory' nodes always have a 'reg' property, and therefore should have a unit-address with just plain hex (i.e. no commas). Fix all the arm64 '/memory' nodes. It's possible that some bootloader depends on /memory (arm32 ATAG to DT code does for example). If so, the memory node should be commented with that requirement. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Chanho Min <chanho.min@lge.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240430191856.874600-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-29Merge tag 'tegra-for-6.10-arm64-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Changes for v6.10-rc1 Adds the Security Engine devices found on Tegra234 and fixes RTC aliases by referencing them by label rather than path so that errors can be detected more easily. * tag 'tegra-for-6.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add Tegra Security Engine DT nodes arm64: tegra: Correct Tegra132 I2C alias Link: https://lore.kernel.org/r/20240426180519.3972626-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-29arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usageRob Herring
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-26arm64: tegra: Add Tegra Security Engine DT nodesAkhil R
Add device tree nodes for Tegra AES and HASH engines. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-04-26arm64: tegra: Correct Tegra132 I2C aliasKrzysztof Kozlowski
There is no such device as "as3722@40", because its name is "pmic". Use phandles for aliases to fix relying on full node path. This corrects aliases for RTC devices and also fixes dtc W=1 warning: tegra132-norrin.dts:12.3-36: Warning (alias_paths): /aliases:rtc0: aliases property is not a valid node (/i2c@7000d000/as3722@40) Fixes: 0f279ebdf3ce ("arm64: tegra: Add NVIDIA Tegra132 Norrin support") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-03-12Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC device tree updates from Arnd Bergmann: "There is very little going on with new SoC support this time, all the new chips are variations of others that we already support, and they are all based on ARMv8 cores: - Mediatek MT7981B (Filogic 820) and MT7988A (Filogic 880) are networking SoCs designed to be used in wireless routers, similar to the already supported MT7986A (Filogic 830). - NXP i.MX8DXP is a variant of i.MX8QXP, with two CPU cores less. These are used in many embedded and industrial applications. - Renesas R8A779G2 (R-Car V4H ES2.0) and R8A779H0 (R-Car V4M) are automotive SoCs. - TI J722S is another automotive variant of its K3 family, related to the AM62 series. There are a total of 7 new arm32 machines and 45 arm64 ones, including - Two Android phones based on the old Tegra30 chip - Two machines using Cortex-A53 SoCs from Allwinner, a mini PC and a SoM development board - A set-top box using Amlogic Meson G12A S905X2 - Eight embedded board using NXP i.MX6/8/9 - Three machines using Mediatek network router chips - Ten Chromebooks, all based on Mediatek MT8186 - One development board based on Mediatek MT8395 (Genio 1200) - Seven tablets and phones based on Qualcomm SoCs, most of them from Samsung. - A third development board for Qualcomm SM8550 (Snapdragon 8 Gen 2) - Three variants of the "White Hawk" board for Renesas automotive SoCs - Ten Rockchips RK35xx based machines, including NAS, Tablet, Game console and industrial form factors. - Three evaluation boards for TI K3 based SoCs The other changes are mainly the usual feature additions for existing hardware, cleanups, and dtc compile time fixes. One notable change is the inclusion of PowerVR SGX GPU nodes on TI SoCs" * tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (824 commits) riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig riscv: dts: starfive: jh7100: fix root clock names ARM: dts: samsung: exynos4412: decrease memory to account for unusable region arm64: dts: qcom: sm8250-xiaomi-elish: set rotation arm64: dts: qcom: sm8650: Fix SPMI channels size arm64: dts: qcom: sm8550: Fix SPMI channels size arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433 arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector dt-bindings: soc: renesas: renesas-soc: Add pattern for gray-hawk dtc: Enable dtc interrupt_provider check arm64: dts: st: add video encoder support to stm32mp255 arm64: dts: st: add video decoder support to stm32mp255 ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk ARM: dts: stm32: enable CRC on stm32mp135f-dk ARM: dts: stm32: add CRC on stm32mp131 ARM: dts: add stm32f769-disco-mb1166-reva09 ARM: dts: stm32: add display support on stm32f769-disco ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco ARM: dts: stm32: add DSI support on stm32f769 ...
2024-02-23arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSIsheetal
Jetson Orin NX and Jetson Orin Nano DTSI files just define the HDA label and it is already added as part of base DTS files. Hence, removing these files. Signed-off-by: sheetal <sheetal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nanosheetal
Add audio support for the NVIDIA Jetson Orin NX (p3767, SKU0) module and Jetson Orin Nano (p3767, SKU5) module Developer Kit with P3768 carrier board. APE and HDA sound cards are enabled. Supported IO interfaces: I2S2 and I2S4. Signed-off-by: sheetal <sheetal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Define missing IO portssheetal
I2S3, I2S5, DMIC1, DMIC2, DMIC4, DSPK1 and DSPK2 IO ports are not defined. Those are not defined earlier because it was inside platform DT and defined only for supported IOs by the platform. Now these are part of SoC DTSI, all IOs ports are defined so that all the ports are available to be used by platforms. Signed-off-by: sheetal <sheetal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Move AHUB ports to SoC DTSIsheetal
AHUB and its child nodes ports are part of platform DTS and with new platform support these entries need to be defined again. As they are common across the platforms, moving them to SoC DTSI to avoid code duplicacy. AHUB HW accelerators are used for audio processing and typically all of these are made available. Platforms can enable all of these just by enabling the AHUB parent device. However IO interfaces (which are also children of AHUB) are selectively enabled based on what the platform actually exposes for interaction with external world. Signed-off-by: sheetal <sheetal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Add USB Type-C controller for Jetson AGX XavierJon Hunter
Populate the Cypress USB Type-C controller for Tegra194 Jetson AGX Xavier board. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Add USB device support for Jetson AGX XavierJon Hunter
Enable the USB device support for the Jetson AGX Xavier platform. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Add current monitors for Jetson XavierJon Hunter
Add the INA3221 current monitors that are present on the Jetson AGX Xavier and Jetson Xavier NX boards. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-02-23arm64: tegra: Add AXI configuration for Tegra234 MGBEThierry Reding
The MGBE devices found on Tegra234 need their AXI interface configured to operate at peak performance. Ideally we would do this in the driver based off the compatible string, but the DT bindings already specify a separate mechanism, so reuse that. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit (git 2.34.1) at 2025-05-31 22:43:39 +0000