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2023-10-23arm64: dts: socionext: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20231023021221.2884828-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-23arm64: dts: Update cache properties for socionextPierre Gondois
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231020195022.4183862-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Add syscon-uhs-mode to SD nodeKunihiko Hayashi
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle of the control logic node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-9-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Add syscon compatible string to soc-glue-debugKunihiko Hayashi
Add "syscon" compatible string to the nodes for soc-glue-debug according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-8-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Add missing reg properties for glue layer nodesKunihiko Hayashi
The nodes for some glue layers don't include necessary reg properties. Add the properties according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-7-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Align node names for SoC-dependent controller and PHYs ↵Kunihiko Hayashi
with bindings The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-6-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Add L2 cache nodeKunihiko Hayashi
Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy information because the following warning was issued. cacheinfo: Unable to detect cache hierarchy for CPU 0 Early cacheinfo failed, ret = -2 Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie nodeKunihiko Hayashi
The generic platform driver pcie-designware-plat.c doesn't work for UniPhier PCIe host controller, because the controller has some necessary initialization sequence for the controller-specific logic. Currently the controller doesn't use "snps,dw-pcie" compatible, so this is no longer needed. Remove the compatible string from the pcie node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-10-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Fix opp-table node name for LD20Kunihiko Hayashi
To fix dtbs_check warning: uniphier-ld20-akebi96.dt.yaml: opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$' From schema: Documentation/devicetree/bindings/opp/opp-v2.yaml Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-9-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Use GIC interrupt definitionsKunihiko Hayashi
Use human-readable definitions for GIC interrupt type and flag, instead of hard-coding the numbers. No functional change. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-6-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controllerKunihiko Hayashi
This "usb-glue" stands for an external controller associated with USB core, however, this is not common. So rename to "usb-controller". Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-4-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-22arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for ↵Kunihiko Hayashi
RTL8211E UniPhier LD20 and PXs3 boards have RTL8211E ethernet phy, and the phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins. After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the delays are working correctly, however, "rgmii" means no delay and the phy doesn't work. So need to set the phy-mode to "rgmii-id" to show that RX/TX delays are enabled. Fixes: c73730ee4c9a ("arm64: dts: uniphier: add AVE ethernet node") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-10arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phyKunihiko Hayashi
This adds missing clock-names and reset-names to pcie-phy node according to Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: add #address-cells and #size-cells to SPI nodesMasahiro Yamada
Documentation/devicetree/bindings/spi/spi-uniphier.txt requires #address-cells and #size-cells, but they are missing in actual DT files. Also, 'make ARCH=arm64 dtbs_check' is really noisy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: Add XDMAC nodeKunihiko Hayashi
Add external DMA controller support implemented in UniPhier SoCs. This supports for LD11, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-17arm64: dts: uniphier: Set SCSSI clock and reset IDs for each channelKunihiko Hayashi
Currently common clock and reset IDs were used, however, each clock and reset ID should be used for each channel. Fixes: 925c5c32f31d ("arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29arm64: dts: uniphier: rename NAND node names to follow json-schemaMasahiro Yamada
Follow the standard nodename pattern "^nand-controller(@.*)?" defined in Documentation/devicetree/bindings/mtd/nand-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm64 dtbs_check' will show warnings like this: nand@68000000: $nodename:0: 'nand@68000000' does not match '^nand-controller(@.*)?' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29arm64: dts: uniphier: rename aidet node names to follow json-schemaMasahiro Yamada
Follow the standard nodename pattern "^interrupt-controller(@[0-9a-f,]+)*$" defined in schemas/interrupt-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm64 dtbs_check' will show warnings like this: aidet@5fc20000: $nodename:0: 'aidet@5fc20000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29arm64: dts: uniphier: change SD/eMMC node names to follow json-schemaMasahiro Yamada
Follow the standard nodename pattern "^mmc(@.*)?$" defined in Documentation/devicetree/bindings/mmc/mmc-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm64 dtbs_check' will show warnings like this: sdhc@5a000000: $nodename:0: 'sdhc@5a000000' does not match '^mmc(@.*)?$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-18arm64: dts: uniphier: add reset-names to NAND controller nodeMasahiro Yamada
The Denali NAND controller IP has separate reset control for the controller core and registers. Add the reset-names, and one more phandle accordingly. This is the approved DT-binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-26arm64: dts: uniphier: add reserved-memory for secure memoryMasahiro Yamada
The memory regions specified by /memreserve/ are passed to early_init_dt_reserve_memory_arch() with nomap=false, so it is not suitable for reserving memory for Trusted Firmware-A etc. Use the more robust /reserved-memory node with the no-map property to prevent the kernel from mapping it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-26arm64: dts: uniphier: update to new Denali NAND bindingMasahiro Yamada
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-15Merge tag 'uniphier-dt64-v5.1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into arm/dt UniPhier ARM64 SoC DT updates for v5.1 - Add PCI Express controller nodes * tag 'uniphier-dt64-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: sort labels in the same order as in dtsi arm64: dts: uniphier: Add PCIe host controller and PHY nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15arm64: dts: uniphier: Add PCIe host controller and PHY nodesKunihiko Hayashi
Add PCIe host controller and PHY nodes. This supports for LD20, PXs3 and their boards. This node defines PCIe memory, I/O, and config spaces as follows. MEM: 20000000-2ffdffff (255MB) I/O: 2ffe0000-2ffeffff ( 64KB) CFG: 2fff0000-2fffffff ( 64KB) Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-01-30arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-12-11arm64: dts: uniphier: Add all CPUs in cooling mapsViresh Kumar
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04arm64: dts: uniphier: Add USB3 controller nodesKunihiko Hayashi
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for LD20, PXs3 and the boards. This includes additional efuse nodes for obtaining PHY trimming values. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03arm64: dts: uniphier: add SD controller nodesMasahiro Yamada
Add SD controller nodes for LD20 and PXs3. LD20 does not support the UHS mode, while PXs3 supports it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3Kunihiko Hayashi
Add nodes of SPI controller for UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28arm64: uniphier: dts: add more clocks to Denali NAND controller nodeMasahiro Yamada
Catch up with the new binding of the Denali IP where three clocks, "nand", "nand_x", "ecc" are required. For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they are both 200MHz. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-19arm64: dts: uniphier: Add missing cooling device properties for CPUsViresh Kumar
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-11Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Olof Johansson: "As always, a large number of DT updates. Too many to enumerate them all, but at a glance: New SoCs introduced in this release: - Amlogic: + Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set top boxes and other products. - Mediatek: + MT7623A, which is a flavor of the MT7623 family with other on-chip ethernet options. - Qualcomm: + SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845 (Cortex-A75/A55 derivative) SoC that's one of the current high-end mobile SoCs. It's great to see mainline support for it. So far, you can't do much with it, since a lot of peripherals are not yet in the DTs but driver support for USB, GPU and other pieces are starting to trickle in. This might end up being a well-supported SoC upstream if the momentum keeps up. - Renesas: + R8A77990, a.k.a R-Car E3, a new automotive entertainment-targeted SoC. Currently only one Cortex-A53 CPU is enabled, we are eagerly awaiting more. So far, basic drivers such as serial, gpios, PMU and ethernet are enabled. + R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR GPU. Same here, basic set of drivers such as serial, gpios and ethernet enabled, and SMP support is also forthcoming. - STMicroelectronics: + STM32F469, very similar tih STM32F429 but with display support Enhancements to SoCs/platforms (DTS contents, some driver portions might not be in yet): - Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc - Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets - Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces - Marvell Berlin2CD: SMP support, thermal sensors - Mediatek MT7623: Highspeed DMA, audio support - Qualcomm IPQ8074 PCIe support, MSM8996 UFS support - Renesas: Watchdog and PMU support across many platforms - Rockchip RK3399: USB3 OTG support - Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3 - STMicro STM32: Lots of peripherals added to STM32MP175C - Uniphier: Ethernet support New boards: - Allwinner A20: Olimex A20-SOM-EVB-eMMC variant - Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version) - Allwinner A33: Nintendo NES/SuperNES Classic Edition - Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune - Berlin2CD: Valve Steam Link - Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1 - Broadcom: Raspberry Pi 3 B+ - Mediatek MT7623N and MT7623A: reference boards - Meson 8M2: Tronsmart MXIII Plus - NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj - Qualcomm MSM8974: Sony Xperia Z1 Compact support - Qualcomm SDM845: MTP development board - Renesas: Ebisu R8A77990 board - Renesas RZ/G1C: iwg23s: iWave G235-SDB - TI am335x: Pocketbeagle support" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits) ARM: dts: aspeed: Fix hwrng register address arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog arm64: dts: sprd: Add GPIO and GPIO keys device nodes arm64: dts: sprd: fix typo in 'remote-endpoint' arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator arm64: dts: fix regulator property name for wlan pcie endpoint arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS ARM: dts: pxa3xx: fix MMC clocks ARM: pxa: dts: add pin definitions for extended GPIOs ARM: pxa: dts: add gpio-ranges to gpio controller ARM: dts: ipq8074: Enable few peripherals for hk01 board ARM: dts: ipq8074: Add pcie nodes ARM: dts: ipq8074: Add peripheral nodes ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi ARM: dts: ipq4019: Change the max opp frequency ...
2018-04-25arm64: dts: uniphier: fix input delay value for legacy mode of eMMCMasahiro Yamada
The property of the legacy mode for the eMMC PHY turned out to be wrong. Some eMMC devices are unstable due to the set-up/hold timing violation. Correct the delay value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-25arm64: dts: uniphier: add syscon-phy-mode property to each ethernet nodeKunihiko Hayashi
Add syscon-phy-mode property specifying a phandle of system controller to each ethernet node. In addition, LD11 SoC has a built-in ethernet PHY. When we set "internal" to phy-mode property, this built-in PHY is available. This patch changes phy-mode property for LD11 to "internal", as default. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-25arm64: dts: uniphier: add clock-names and reset-names to ethernet nodeKunihiko Hayashi
Add clock-names and reset-names because this node recognizes multiple clocks and resets. ("ether", and so on, for each) Suggested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-21arm64: dts: uniphier: add syscon property for UniPhier sound systemKatsuhiro Suzuki
This patch adds syscon property for specifying soc-glue core into device-tree of LD11/LD20 SoC. Currently, soc-glue core is used for changing the state of S/PDIF signal output pin to signal output state or Hi-Z state. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15arm64: dts: uniphier: use proper SPDX-License-Identifier styleMasahiro Yamada
According to Documentation/process/license-rules.rst, move the SPDX License Identifier to the very top of the file. I used C++ comment style not only for the SPDX line but for the entire block because this seems Linus' preference [1]. I also dropped the parentheses to follow the examples in that document. [1] https://lkml.org/lkml/2017/11/25/133 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15arm64: dts: uniphier: add AVE ethernet nodeKunihiko Hayashi
Add nodes of the AVE ethernet controller for LD11 and LD20 SoCs and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15arm64: dts: uniphier: add sound nodeKatsuhiro Suzuki
This patch adds audio controller, codec and simple card node of UniPhier AIO sound system for LD11/20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-12arm64: dts: uniphier: use macros in dt-bindings headerMasahiro Yamada
The dt-bindings header was applied to the driver subsystem. I had to wait for a merge window to use it from DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-24arm64: dts: uniphier: add resets propertiesMasahiro Yamada
Add resets properties to all nodes that have reset lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-24arm64: dts: uniphier: add eMMC hardware reset provider nodeMasahiro Yamada
Add mmc-pwrseq-emmc node to perform standard eMMC hardware reset procedure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-24arm64: dts: uniphier: add GPIO controller nodesMasahiro Yamada
The GPIO controller also acts as an interrupt controller and the interrupt lines are connected to the AIDET block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-24arm64: dts: uniphier: fix W=2 build warningsMasahiro Yamada
Fix warnings like follows: Warning (node_name_chars_strict): Character '_' not recommended in ... Commit 8654cb8d0371 ("dtc: update warning settings for new bus and node/property name checks") says these checks are a bit subjective, but Rob also says to not add new W=2 warnings. The exising warnings should be fixed in order to catch new ones easily. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23arm64: dts: uniphier: add efuse node for LD11, LD20, and PXs3Keiji Hayashibara
Add efuse node for UniPhier LD11, LD20, and PXs3. This efuse node is included in soc-glue. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15arm64: dts: uniphier: add nodes of thermal monitor and thermal zone for LD20Kunihiko Hayashi
Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC. The thermal monitor node is included in sysctrl. Since the efuse might not have a calibrated value of thermal monitor, this patch gives the default value for LD20. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28arm64: dts: uniphier: fix size of sdctrl nodeMasahiro Yamada
All registers are located within 0x400 size from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28arm64: dts: uniphier: add AIDET nodesMasahiro Yamada
Add UniPhier AIDET (ARM Interrupt Detector) nodes to support active low interrupts. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26arm64: dts: uniphier: add reset controller node of analog amplifierKatsuhiro Suzuki
This patch adds reset controller node of analog signal amplifier core (ADAMV) for UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>