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2024-04-26arm64: tegra: Correct Tegra132 I2C aliasKrzysztof Kozlowski
There is no such device as "as3722@40", because its name is "pmic". Use phandles for aliases to fix relying on full node path. This corrects aliases for RTC devices and also fixes dtc W=1 warning: tegra132-norrin.dts:12.3-36: Warning (alias_paths): /aliases:rtc0: aliases property is not a valid node (/i2c@7000d000/as3722@40) Fixes: 0f279ebdf3ce ("arm64: tegra: Add NVIDIA Tegra132 Norrin support") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Enable IOMMU for host1x on Tegra132Rayyan Ansari
Add the iommu property to the host1x node to register it with its swgroup. Signed-off-by: Rayyan Ansari <rayyan@ansari.sh> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-03arm64: tegra: Drop serial clock-names and reset-namesKrzysztof Kozlowski
The serial node does not use clock-names and reset-names: tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Sort nodes by unit-address, then alphabeticallyThierry Reding
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first. These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance"). While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unneeded clock-names for Tegra132 PWMThierry Reding
There's only a single clock for this IP block, so it doesn't need a clock-names property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename thermal zones nodesThierry Reding
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Sort Tegra132 XUSB clocks correctlyThierry Reding
Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Drop unused AHCI clocks on Tegra132Thierry Reding
The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra132 I2C compatible string listThierry Reding
The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add OPP tables on Tegra132Thierry Reding
Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix compatible string for Tegra132 timerThierry Reding
The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Remove useless usb-ehci compatible stringThierry Reding
There's no such thing as a generic USB EHCI controller. The EHCI controllers found on Tegra SoCs are instantiations that need Tegra- specific glue to work properly, so drop the generic compatible string and keep only the Tegra-specific ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-04arm64: tegra: Add new USB PHY properties on Tegra132Dmitry Osipenko
Add new properties to USB PHYs needed for enabling USB OTG mode. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13arm64: tegra: Fix compatible string for Tegra132 CPUsThierry Reding
The documented compatible string for the CPUs found on Tegra132 is "nvidia,tegra132-denver", rather than the previously used compatible string "nvidia,denver". Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210Sowjanya Komatineni
Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERMThierry Reding
For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet <kwizart@gmail.com> Suggested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zonesNicolas Chauvet
According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add i2c-bus subnode for DPAUX controllersThierry Reding
The DPAUX controller device tree bindings require the bus to have an i2c-bus subnode to distinguish between I2C clients and pinmux groups. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix indentation in Tegra132 device treeThierry Reding
Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add missing #phy-cells property to USB PHYsThierry Reding
USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Tegra132 EMC is not compatible with Tegra124Thierry Reding
The external memory controller found on Tegra132 is not fully compatible with the instantiation on Tegra124, so remove the corresponding string from the list of compatible strings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use sor0_out clock on Tegra132Thierry Reding
The sor0_out clock is required to make eDP work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark host1x as simple busThierry Reding
The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use proper tuple notationThierry Reding
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-13arm64: tegra: Enable XUSB on NorrinThierry Reding
Use the XUSB controller instead of the legacy EHCI controller to enable USB 3.0 support. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Rename sdhci nodes to mmcThierry Reding
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove parent clock from display controllersThierry Reding
The display controller's parent clock depends on the output that's consuming data from the display controller, so it needs to be specified as the parent of the corresponding output. The device tree bindings do specify this, so just correct the existing device trees that get this wrong. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt-names for host1xThierry Reding
Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add Tegra132 compatible string for host1xThierry Reding
While the host1x controller found on Tegra132 is the same as on Tegra124 it is good practice to also list a SoC-specific compatible string so any SoC-specific quirks can be implemented in drivers if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add clock-cells property to Tegra PMC nodeSowjanya Komatineni
Tegra132 and Tegra210 PMC blocks have clk_out_1, clk_out_2, clk_out_3, and a blink clock as a part of the PMC. These clocks were erroneously provided by the clock and reset controller and are now provided by the PMC instead because that's where the primary controls are. Clock IDs for these clocks are defined in the PMC dt-bindings. This patch updates the device tree to include the PMC dt-bindings header and adds the #clock-cells property with one clock specifier to the PMC node. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Rename EMC on Tegra132Thierry Reding
Rename the EMC node to external-memory-controller according to device tree best practices. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Let the EMC hardware use the EMC clockThierry Reding
The EMC hardware block needs access to the EMC clock in order to scale the external memory frequency. Add the clocks property so that drivers for the EMC can acquire a reference to the EMC clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-30arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-13arm64: dts: nvidia: fix PCI bus dtc warningsRob Herring
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04arm64: tegra: Update the Tegra132 flowctrl compatible stringJon Hunter
Update the Tegra132 flowctrl compatible string to include "nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-27arm64: tegra: set hot trips for Tegra132Wei Ni
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set critical trips for Tegra132Wei Ni
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra132, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: use tegra132-soctherm for Tegra132Wei Ni
The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-04-11arm64: tegra: Fix copy/paste typo in several DTS includesThierry Reding
The comment about the 8250 vs. APB DMA-enabled UART devices that was added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts: add aliases and DMA requestor for serial controller") introduced a typo that has since spread to various other DTS include files. Fix all occurrences of this typo. Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Remove 0, prefix from unit-addressesThierry Reding
When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-04arm64: Fix misspellings in comments.Adam Buchbinder
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-11-24arm64: tegra: Add Tegra132 supportThierry Reding
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124 but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI file for the SoC, which is mostly similar to the one for Tegra124. Based on work by Allen Martin <amartin@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>