diff options
Diffstat (limited to 'arch/arm64/boot/dts/rockchip')
108 files changed, 17013 insertions, 1179 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index def1222c1907..4bf84622db47 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,10 +1,18 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-cobra-ltk050h3146w-a2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-cobra-ltk050h3146w.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-cobra-ltk050h3148w.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-cobra-ltk500hd1829.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-firefly-jd4-core-mb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-pp1516-ltk050h3146w-a2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-pp1516-ltk050h3148w.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-lvds-9904379.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-bpi-p2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb @@ -38,6 +46,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb @@ -61,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb @@ -78,6 +88,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb @@ -122,6 +133,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb @@ -132,6 +144,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb @@ -141,21 +155,27 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-max.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-ultra.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb @@ -170,3 +190,61 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb + +# Overlay application tests +# +# A .dtbo must have its own +# +# dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay>.dtbo +# +# entry, and at least one overlay application test reflecting a possible +# hardware combination in real life: +# +# dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay-application-test>.dtb +# <overlay-application-test>-dtbs := <base>.dtb <overlay-1>.dtbo [<overlay-2>.dtbo ...] +# +# This will make the <base>.dtb have symbols (like when DTC_FLAGS has -@ passed) +# and generate a new DTB (<overlay-application-test>.dtb) which is the +# result of the application of <overlay-1>.dtbo and other listed overlays on top +# of <base>.dtb. + +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-lvds-9904379.dtb +px30-ringneck-haikou-haikou-lvds-9904379-dtbs := px30-ringneck-haikou.dtb \ + px30-ringneck-haikou-lvds-9904379.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb +px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \ + px30-ringneck-haikou-video-demo.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-haikou-video-demo.dtb +rk3399-puma-haikou-haikou-video-demo-dtbs := rk3399-puma-haikou.dtb \ + rk3399-puma-haikou-video-demo.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb +rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \ + rk3568-wolfvision-pf5-display-vz.dtbo \ + rk3568-wolfvision-pf5-io-expander.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \ + rk3588-edgeble-neu6a-wifi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-wifi.dtb +rk3588-edgeble-neu6b-wifi-dtbs := rk3588-edgeble-neu6b-io.dtb \ + rk3588-edgeble-neu6a-wifi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtb +rk3588-jaguar-pre-ict-tester-dtbs := rk3588-jaguar.dtb \ + rk3588-jaguar-pre-ict-tester.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtb +rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \ + rk3588-rock-5b-pcie-ep.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb +rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ + rk3588-rock-5b-pcie-srns.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb +rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ + rk3588-tiger-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts new file mode 100644 index 000000000000..1d26164be7b8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model = "Theobroma Systems Cobra with LTK050H3146W-A2 Display"; + compatible = "tsd,px30-cobra-ltk050h3146w-a2", "tsd,px30-cobra", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3146w-a2"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&dsp_rst>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts new file mode 100644 index 000000000000..82c6acdb4fae --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model = "Theobroma Systems Cobra with LTK050H3146W Display"; + compatible = "tsd,px30-cobra-ltk050h3146w", "tsd,px30-cobra", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3146w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&dsp_rst>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts new file mode 100644 index 000000000000..94449132df38 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model = "Theobroma Systems Cobra with ltk050h3148w Display"; + compatible = "tsd,px30-cobra-ltk050h3148w", "tsd,px30-cobra", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&dsp_rst>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts new file mode 100644 index 000000000000..d7b639e7ccab --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model = "Theobroma Systems Cobra prototype with LTK500HD1829 Display"; + compatible = "tsd,px30-cobra-ltk500hd1829", "tsd,px30-cobra", "rockchip,px30"; + + aliases { + mmc1 = &sdmmc; + }; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk500hd1829"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&dsp_rst>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&cobra_pin_hog>, <&cobra_proto_hog>; + + hog { + cobra_proto_hog: cobra-proto-hog { + rockchip,pins = + /* STUSB4500 open drain outout POWER_OK2, needs pull-up */ + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + /* STUSB4500 open drain outout POWER_OK3, needs pull-up */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + broken-cd; + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vccio_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi new file mode 100644 index 000000000000..b7e669d8ba4d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi @@ -0,0 +1,566 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "px30.dtsi" + +/ { + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial5:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc5v0_sys>; + pwms = <&pwm0 0 25000 0>; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&pwm1 0 1000 0>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&heartbeat_led_pin>; + + /* + * LED14 on the PCB. Typically NOT populated. + */ + led-0 { + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "heartbeat"; + linux,default-trigger = "heartbeat"; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + ring_red: led-0 { + color = <LED_COLOR_ID_RED>; + default-state = "off"; + label = "ring_red"; + pwms = <&pwm5 0 1000000 0>; + max-brightness = <255>; + }; + + ring_green: led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + label = "ring_green"; + pwms = <&pwm6 0 1000000 0>; + max-brightness = <255>; + }; + + ring_blue: led-2 { + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + label = "ring_blue"; + pwms = <&pwm7 0 1000000 0>; + max-brightness = <255>; + }; + }; + + /* also named 5V_Q7 in schematics */ + vcc5v0_sys: regulator-vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + /* + * For hs200 support, U-Boot would have to set the RK809 DCDC4 + * rail to 1.8V from the default of 3.0V. It doesn't do that on + * devices out in the field, so disable hs200. + * mmc-hs200-1_8v; + */ + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_emmc>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-handle = <&dp83825>; + phy-supply = <&vcc_3v3>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_log>; + status = "okay"; +}; + +/* I2C0 = PMIC, STUSB4500, RTC */ +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3>; + vcc6-supply = <&vcc_3v3>; + vcc7-supply = <&vcc_3v3>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name = "vcc_3v0_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_2v8: LDO_REG4 { + regulator-name = "vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + /* + * vccio_sd also supplies the vmmc supply on prototypes + * with sd-slots, so needs to stay single voltage for + * those. Production models don't have sd-slots anymore + * and only supply vccio2 from this regulator. + */ + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + /* vcc_sdio also supplies the pull-up resistors for i2c1 */ + vcc_sdio: LDO_REG6 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-name = "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name = "vcc_1v8_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + status = "okay"; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + AVDD28-supply = <&vcc_2v8>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tch_int &tch_rst>; + reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + VDDIO-supply = <&vcc_3v3>; + }; +}; + +/* + * Enable pull-ups to prevent floating pins when the touch + * panel is not connected. + */ +&i2c2_xfer { + rockchip,pins = + <2 RK_PB7 2 &pcfg_pull_up>, + <2 RK_PC0 2 &pcfg_pull_up>; +}; + +&io_domains { + vccio1-supply = <&vcc_sdio>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_emmc>; + status = "okay"; +}; + +&mdio { + dp83825: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + reset-assert-us = <50000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&cobra_pin_hog>; + + hog { + cobra_pin_hog: cobra-pin-hog { + rockchip,pins = + /* USB_HUB2_RESET */ + <0 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, + /* USB_HUB1_RESET */ + <0 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>, + /* The default pull-down can keep the IC in reset. */ + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + /* USB-A 5V enable */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_output_high>, + /* USB-A data enable */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + phy_rst: phy-rst { + rockchip,pins = + <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + heartbeat_led_pin: heartbeat-led-pin { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + panel { + dsp_rst: dsp-rst { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + tch_int: tch-int { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tch_rst: tch-rst { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart1 { + /delete-property/ dmas; + /delete-property/ dma-names; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5_xfer>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "disabled"; +}; + +&vopl_mmu { + status = "disabled"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 1edfd643b25a..a334ef0629d1 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -31,7 +31,7 @@ }; vcc3v3_btreg: vcc3v3-btreg { - compatible = "regulator-gpio"; + compatible = "regulator-fixed"; enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&bt_enable_h>; @@ -39,7 +39,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - states = <3300000 0x0>; }; vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod { diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index 80db778c9684..b60e68faa83a 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -26,5 +26,5 @@ }; &vcc3v3_btreg { - enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index 165d09ccb942..5886b802c520 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -39,5 +39,5 @@ }; &vcc3v3_btreg { - enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts new file mode 100644 index 000000000000..b71929bcb33e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-pp1516.dtsi" + +/ { + model = "Theobroma Systems PP-1516 with LTK050H3146W-A2 Display"; + compatible = "tsd,px30-pp1516-ltk050h3146w-a2", "tsd,px30-pp1516", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3146w-a2"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&dsp_rst>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts new file mode 100644 index 000000000000..a9bd5936c701 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-pp1516.dtsi" + +/ { + model = "Theobroma Systems PP-1516 with LTK050H3148W Display"; + compatible = "tsd,px30-pp1516-ltk050h3148w", "tsd,px30-pp1516", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&dsp_rst>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi new file mode 100644 index 000000000000..3f9a133d7373 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi @@ -0,0 +1,602 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "px30.dtsi" + +/ { + aliases { + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial5:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc5v0_sys>; + pwms = <&pwm0 0 25000 0>; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&pwm1 0 1000 0>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&debug_led_pin>, <&heartbeat_led_pin>; + + /* + * LED2 on the PCB, left of the USB-C connector. + * Typically NOT populated. + */ + debug: led-0 { + label = "debug"; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + + /* + * LED14 on the PCB, left of the PX30 SoC. + * Typically NOT populated. + */ + heartbeat: led-1 { + label = "heartbeat"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc5v0_sys: regulator-vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_cam_avdd: regulator-vcc-cam-avdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_cam_avdd"; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_avdd_en>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_2v8>; + }; + + vcc_cam_dovdd: regulator-vcc-cam-dovdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_cam_dovdd"; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_dovdd_en>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc_cam_dvdd: regulator-vcc-cam-dvdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_cam_dvdd"; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&cam_dvdd_en>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_lens_afvdd: regulator-vcc-lens-afvdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lens_afvdd"; + gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_afvdd_en>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_2v8>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&csi_dphy { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + /* + * For hs200 support, U-Boot would have to set the RK809 DCDC4 + * rail to 1.8V from the default of 3.0V. It doesn't do that on + * devices out in the field, so disable hs200. + * mmc-hs200-1_8v; + */ + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_emmc>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_log>; + status = "okay"; +}; + +/* I2C0 = PMIC, Touchscreen */ +&i2c0 { + status = "okay"; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + AVDD28-supply = <&vcc_2v8>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tch_int &tch_rst>; + reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vcc_3v3>; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3>; + vcc6-supply = <&vcc_3v3>; + vcc7-supply = <&vcc_3v3>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name = "vcc_3v0_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_2v8: LDO_REG4 { + regulator-name = "vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_sdio: LDO_REG6 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-name = "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name = "vcc_1v8_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +/* I2C2 = Accelerometer + Camera */ +&i2c2 { + /* MEMSIC MXC4005 accelerometer is rated for I2C Fast Mode (<=400KHz) */ + /* OmniVision OV5675 camera is rated for I2C Fast Mode (<=400KHz) */ + clock-frequency = <400000>; + status = "okay"; + + focus: focus@c { + compatible = "dongwoon,dw9714"; + reg = <0xc>; + vcc-supply = <&vcc_lens_afvdd>; + }; + + accel@15 { + compatible = "memsic,mxc4005"; + reg = <0x15>; + interrupt-parent = <&gpio2>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_int>; + }; + + camera@36 { + compatible = "ovti,ov5675"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + assigned-clocks = <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <19200000>; + avdd-supply = <&vcc_cam_avdd>; + dvdd-supply = <&vcc_cam_dvdd>; + dovdd-supply = <&vcc_cam_dovdd>; + lens-focus = <&focus>; + orientation = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &cam_pwdn>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rotation = <0>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <450000000>; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_sdio>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_emmc>; + status = "okay"; +}; + +&isp { + status = "okay"; + + ports { + port@0 { + mipi_in_ucam: endpoint@0 { + reg = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ucam_out>; + }; + }; + }; +}; + +&isp_mmu { + status = "okay"; +}; + +&pinctrl { + accel { + accel_int: accel-int { + rockchip,pins = + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + camera { + cam_afvdd_en: cam-afvdd-en { + rockchip,pins = + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_avdd_en: cam-avdd-en { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_dovdd_en: cam-dovdd-en { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_dvdd_en: cam-dvdd-en { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_pwdn: cam-pwdn { + rockchip,pins = + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + debug_led_pin: debug-led-pin { + rockchip,pins = + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + heartbeat_led_pin: heartbeat-led-pin { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + panel { + dsp_rst: dsp-rst { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + tch_int: tch-int { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tch_rst: tch-rst { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5_xfer>; + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso new file mode 100644 index 000000000000..3fc088a5636a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * HAIKOU-LVDS-9904379 adapter for PX30 Ringneck and Haikou carrierboard. + * + * This adapter needs to be plugged in the fake PCIe connector called Video + * Connector on Haikou carrierboard. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + brightness-levels = <0 255>; + default-brightness-level = <255>; + num-interpolated-steps = <255>; + power-supply = <&vcc3v3_baseboard>; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "admatec,9904379", "panel-lvds"; + backlight = <&backlight_lvds>; + data-mapping = "vesa-24"; + height-mm = <126>; + power-supply = <&vcc3v3_baseboard>; + width-mm = <224>; + + panel-timing { + clock-frequency = <49500000>; + hactive = <1024>; + hback-porch = <90>; + hfront-porch = <90>; + hsync-len = <90>; + vactive = <600>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <10>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* EEPROM and GT928 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int &touch_rst>; + pinctrl-names = "default"; + touchscreen-inverted-x; + touchscreen-inverted-y; + AVDD28-supply = <&vcc3v3_baseboard>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + eeprom@54 { + reg = <0x54>; + compatible = "st,24c04", "atmel,24c04"; + pagesize = <16>; + size = <512>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&lvds { + status = "okay"; +}; + +&lvds_out { + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; +}; + +&pinctrl { + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso new file mode 100644 index 000000000000..7d9ea5aa5984 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Ringneck system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/px30-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts index eb9470a00e54..91cf4cd3fae2 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -154,6 +154,8 @@ }; &i2c3 { + status = "okay"; + eeprom@50 { reg = <0x50>; compatible = "atmel,24c01"; @@ -194,6 +196,13 @@ <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + uart { + uart5_rts_pin: uart5-rts-pin { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm0 { @@ -222,10 +231,15 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; &uart5 { + /* Add pinmux for rts-gpios (uart5_rts_pin) */ + pinctrl-names = "default"; + pinctrl-0 = <&uart5_xfer &uart5_rts_pin>; rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi index e80412abec08..ab232e5c7ad6 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -83,9 +83,7 @@ /* On-module TI DP83825I PHY but no connector, enable in carrierboard */ &gmac { - snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; + phy-handle = <&dp83825>; phy-supply = <&vcc_3v3>; clock_in_out = "output"; }; @@ -325,10 +323,6 @@ }; }; -&i2c3 { - status = "okay"; -}; - &i2s0_8ch { rockchip,trcm-sync-tx-only; @@ -348,6 +342,18 @@ status = "okay"; }; +&mdio { + dp83825: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + reset-assert-us = <50000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -355,6 +361,12 @@ }; }; + ethernet { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pin: module-led-pin { rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 9137dd76e72c..feabdadfa440 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -985,6 +985,12 @@ resets = <&cru SRST_GMAC_A>; reset-names = "stmmaceth"; status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; }; sdmmc: mmc@ff370000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts index 629121de5a13..5e7181948992 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts @@ -147,7 +147,7 @@ &pwm5 { status = "okay"; - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm5_pin_pull_down>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts index a94114fb7cc1..96c27fc5005d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts @@ -274,13 +274,13 @@ &pwm0 { pinctrl-0 = <&pwm0_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; &pwm1 { pinctrl-0 = <&pwm1_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts index 6310b58de77f..a4bdd87d0729 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts @@ -428,10 +428,18 @@ status = "okay"; }; +&u2phy_otg { + status = "okay"; +}; + &uart2 { status = "okay"; }; +&usb20_otg { + status = "okay"; +}; + &usbdrd3 { dr_mode = "host"; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index e550b6eeeff3..5367e5fa9232 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -343,6 +343,7 @@ /* maximum speed for Rockchip SPI */ spi-max-frequency = <50000000>; + vcc-supply = <&vcc_io>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts new file mode 100644 index 000000000000..70aee1ab904c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3399.dtsi" + +/ { + model = "Rockchip RK3399 EVB IND LPDDR4 Board"; + compatible = "rockchip,rk3399-evb-ind", "rockchip,rk3399"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <4>; + i2c-scl-rising-time-ns = <168>; + status = "okay"; + + vdd_gpu: regulator@10 { + compatible = "tcs,tcs4525"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <712500>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_b: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <712500>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <750000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <750000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2200000>; + regulator-min-microvolt = <2200000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-name = "vcc0v9_soc"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-name = "vdd1v5_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-name = "vccio_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcca_1v8>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1 { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2 { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + keep-power-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts index 9e4b12ed62cb..be3ae473e562 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts @@ -36,6 +36,6 @@ compatible = "qcom,ath10k"; reg = <0x00000000 0x0 0x00000000 0x0 0x00000000>, <0x03000010 0x0 0x00000000 0x0 0x00200000>; - qcom,ath10k-calibration-variant = "GO_DUMO"; + qcom,calibration-variant = "GO_DUMO"; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi index b1c9bd0e63ef..8d94d9f91a5c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi @@ -115,7 +115,7 @@ }; &u2phy1_host { - status = "disabled"; + phy-supply = <&vdd_5v>; }; &uart0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index b169be06d4d1..c8eb5481f43d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -603,7 +603,7 @@ }; &pwm2 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin_pull_down>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso new file mode 100644 index 000000000000..0377ec860d35 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Puma system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rk3399-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 947bbd62a6b0..70979079923c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -149,8 +149,15 @@ }; }; +&gmac { + status = "okay"; +}; + &hdmi { - ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { status = "okay"; }; @@ -186,9 +193,22 @@ }; }; -&i2c6 { +&i2c7 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s2 { status = "okay"; - clock-frequency = <400000>; }; &pcie_phy { @@ -292,14 +312,6 @@ status = "okay"; }; -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - &vopb { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 995b30a7aae0..587e89d7fc5e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -60,16 +60,6 @@ vin-supply = <&vcc5v0_sys>; }; - vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - vcc5v0_sys: regulator-vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -183,7 +173,6 @@ snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x10>; rx_delay = <0x23>; - status = "okay"; }; &gpu { @@ -389,6 +378,14 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; +}; + +&i2c6 { + clock-frequency = <400000>; +}; + &i2c7 { status = "okay"; clock-frequency = <400000>; @@ -439,7 +436,6 @@ pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - status = "okay"; }; /* @@ -521,10 +517,10 @@ }; }; - usb2 { - vcc5v0_host_en: vcc5v0-host-en { + usb { + cy3304_reset: cy3304-reset { rockchip,pins = - <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + <4 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; }; }; @@ -589,11 +585,6 @@ u2phy1_otg: otg-port { status = "okay"; }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; }; &usbdrd3_1 { @@ -603,12 +594,27 @@ &usbdrd_dwc3_1 { status = "okay"; dr_mode = "host"; -}; + pinctrl-names = "default"; + pinctrl-0 = <&cy3304_reset>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vdd-supply = <&vcc1v2_phy>; + vdd2-supply = <&vcc3v3_sys>; -&usb_host1_ehci { - status = "okay"; -}; + }; -&usb_host1_ohci { - status = "okay"; + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vdd-supply = <&vcc1v2_phy>; + vdd2-supply = <&vcc3v3_sys>; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index e2e9279fa267..8e3858cf988c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -112,7 +112,7 @@ &i2c1 { es8388: es8388@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index 0393da25cdfb..fc9279627ef6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -736,6 +736,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <30000000>; + vcc-supply = <&vcc3v3_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 541dca12bf1a..046dbe329017 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -43,7 +43,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; - clock-names = "lpo"; + clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi index 69a9d6170649..a7e4adf87e7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi @@ -227,6 +227,16 @@ vin-supply = <&vcc12v_dcin>; }; + vcca_0v9: regulator-vcca-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + vdd_log: regulator-vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; @@ -312,6 +322,8 @@ }; &hdmi { + avdd-0v9-supply = <&vcca_0v9>; + avdd-1v8-supply = <&vcc1v8_dvp>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; @@ -661,6 +673,8 @@ num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_perst>; + vpcie0v9-supply = <&vcca_0v9>; + vpcie1v8-supply = <&vcca_1v8>; vpcie12v-supply = <&vcc12v_dcin>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; @@ -836,6 +850,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; + vcc-supply = <&vcc_3v0>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi new file mode 100644 index 000000000000..ea051362fb26 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi @@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + arm { + /omit-if-no-ref/ + arm_pins: arm-pins { + rockchip,pins = + /* arm_avs */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clkm0_32k_out: clkm0-32k-out { + rockchip,pins = + /* clkm0_32k_out */ + <3 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clkm1_32k_out: clkm1-32k-out { + rockchip,pins = + /* clkm1_32k_out */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PD6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + eth_pins: eth-pins { + rockchip,pins = + /* eth_clk_25m_out */ + <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + fephy { + /omit-if-no-ref/ + fephym0_led_dpx: fephym0-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_link: fephym0-led_link { + rockchip,pins = + /* fephy_led_link_m0 */ + <4 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_spd: fephym0-led_spd { + rockchip,pins = + /* fephy_led_spd_m0 */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_dpx: fephym1-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_link: fephym1-led_link { + rockchip,pins = + /* fephy_led_link_m1 */ + <2 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_spd: fephym1-led_spd { + rockchip,pins = + /* fephy_led_spd_m1 */ + <2 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD5 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmi_pins: hdmi-pins { + rockchip,pins = + /* hdmi_tx_cec */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* hdmi_tx_hpd */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* hdmi_tx_scl */ + <0 RK_PA4 1 &pcfg_pull_none>, + /* hdmi_tx_sda */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + hsm { + /omit-if-no-ref/ + hsmm0_pins: hsmm0-pins { + rockchip,pins = + /* hsm_clk_out_m0 */ + <2 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hsmm1_pins: hsmm1-pins { + rockchip,pins = + /* hsm_clk_out_m1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <4 RK_PC4 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <4 RK_PC3 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PA1 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PA0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <4 RK_PA3 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <4 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PC5 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PC6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <1 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <1 RK_PA6 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PA0 2 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PA1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PC1 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4_xfer: i2c4-xfer { + rockchip,pins = + /* i2c4_scl */ + <2 RK_PA0 4 &pcfg_pull_none_smt>, + /* i2c4_sda */ + <2 RK_PA1 4 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <1 RK_PB2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <1 RK_PB3 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PD2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <3 RK_PB2 5 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <3 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PD4 3 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PD7 3 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7_xfer: i2c7-xfer { + rockchip,pins = + /* i2c7_scl */ + <2 RK_PA5 4 &pcfg_pull_none_smt>, + /* i2c7_sda */ + <2 RK_PA6 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi: i2s0m0-sdi { + rockchip,pins = + /* i2s0m0_sdi */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m0_sdo: i2s0m0-sdo { + rockchip,pins = + /* i2s0m0_sdo */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi: i2s0m1-sdi { + rockchip,pins = + /* i2s0m1_sdi */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m1_sdo: i2s0m1-sdo { + rockchip,pins = + /* i2s0m1_sdo */ + <1 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1_lrck: i2s1-lrck { + rockchip,pins = + /* i2s1_lrck */ + <4 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_mclk: i2s1-mclk { + rockchip,pins = + /* i2s1_mclk */ + <4 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sclk: i2s1-sclk { + rockchip,pins = + /* i2s1_sclk */ + <4 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sdi0: i2s1-sdi0 { + rockchip,pins = + /* i2s1_sdi0 */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi1: i2s1-sdi1 { + rockchip,pins = + /* i2s1_sdi1 */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi2: i2s1-sdi2 { + rockchip,pins = + /* i2s1_sdi2 */ + <4 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi3: i2s1-sdi3 { + rockchip,pins = + /* i2s1_sdi3 */ + <4 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo0: i2s1-sdo0 { + rockchip,pins = + /* i2s1_sdo0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo1: i2s1-sdo1 { + rockchip,pins = + /* i2s1_sdo1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo2: i2s1-sdo2 { + rockchip,pins = + /* i2s1_sdo2 */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo3: i2s1-sdo3 { + rockchip,pins = + /* i2s1_sdo3 */ + <4 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_tck_m0 */ + <2 RK_PA2 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m0 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* jtag_mcu_tms_m0 */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_tck_m1 */ + <4 RK_PD0 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m1 */ + <4 RK_PC7 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m1 */ + <4 RK_PD0 3 &pcfg_pull_none>, + /* jtag_mcu_tms_m1 */ + <4 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + pcie { + /omit-if-no-ref/ + pciem0_pins: pciem0-pins { + rockchip,pins = + /* pcie_clkreqn_m0 */ + <3 RK_PA6 5 &pcfg_pull_none>, + /* pcie_perstn_m0 */ + <3 RK_PB0 5 &pcfg_pull_none>, + /* pcie_waken_m0 */ + <3 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pciem1_pins: pciem1-pins { + rockchip,pins = + /* pcie_clkreqn_m1 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie_perstn_m1 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie_waken_m1 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdm_clk0: pdm-clk0 { + rockchip,pins = + /* pdm_clk0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_clk1: pdm-clk1 { + rockchip,pins = + /* pdm_clk1 */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi0: pdm-sdi0 { + rockchip,pins = + /* pdm_sdi0 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + /* pdm_sdi1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + /* pdm_sdi2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + /* pdm_sdi3 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <4 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + refm0_pins: refm0-pins { + rockchip,pins = + /* ref_clk_out_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + refm1_pins: refm1-pins { + rockchip,pins = + /* ref_clk_out_m1 */ + <3 RK_PC3 6 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmii_miim: rgmii-miim { + rockchip,pins = + /* rgmii_mdc */ + <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_mdio */ + <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rx_bus2: rgmii-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_rxd1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_rxdv_crs */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_tx_bus2: rgmii-tx_bus2 { + rockchip,pins = + /* rgmii_txd0 */ + <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd1 */ + <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txen */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_clk: rgmii-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_txclk */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_bus: rgmii-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_rxd3 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_txd2 */ + <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd3 */ + <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_clk: rgmii-clk { + rockchip,pins = + /* rgmii_clk */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmii_txer: rgmii-txer { + rockchip,pins = + /* rgmii_txer */ + <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scrm0_pins: scrm0-pins { + rockchip,pins = + /* scr_clk_m0 */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_data_m0 */ + <1 RK_PA1 3 &pcfg_pull_none>, + /* scr_detn_m0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* scr_rstn_m0 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + scrm1_pins: scrm1-pins { + rockchip,pins = + /* scr_clk_m1 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* scr_data_m1 */ + <2 RK_PA3 4 &pcfg_pull_none>, + /* scr_detn_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* scr_rstn_m1 */ + <2 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + sdio0 { + /omit-if-no-ref/ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + /* sdio0_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_clk: sdio0-clk { + rockchip,pins = + /* sdio0_clk */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_cmd: sdio0-cmd { + rockchip,pins = + /* sdio0_cmd */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_det: sdio0-det { + rockchip,pins = + /* sdio0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio0_pwren: sdio0-pwren { + rockchip,pins = + /* sdio0_pwren */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sdio1 { + /omit-if-no-ref/ + sdio1_bus4: sdio1-bus4 { + rockchip,pins = + /* sdio1_d0 */ + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d1 */ + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d2 */ + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d3 */ + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_clk: sdio1-clk { + rockchip,pins = + /* sdio1_clk */ + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_cmd: sdio1-cmd { + rockchip,pins = + /* sdio1_cmd */ + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_det: sdio1-det { + rockchip,pins = + /* sdio1_det */ + <3 RK_PB3 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio1_pwren: sdio1-pwren { + rockchip,pins = + /* sdio1_pwren */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_detn */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <4 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <4 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0_pins: spi0-pins { + rockchip,pins = + /* spi0_clk */ + <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>, + /* spi0_miso */ + <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>, + /* spi0_mosi */ + <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi0_csn0: spi0-csn0 { + rockchip,pins = + /* spi0_csn0 */ + <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi0_csn1: spi0-csn1 { + rockchip,pins = + /* spi0_csn1 */ + <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1_pins: spi1-pins { + rockchip,pins = + /* spi1_clk */ + <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* spi1_miso */ + <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>, + /* spi1_mosi */ + <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi1_csn0: spi1-csn0 { + rockchip,pins = + /* spi1_csn0 */ + <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi1_csn1: spi1-csn1 { + rockchip,pins = + /* spi1_csn1 */ + <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>; + }; + }; + + tsi0 { + /omit-if-no-ref/ + tsi0_pins: tsi0-pins { + rockchip,pins = + /* tsi0_clkin */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* tsi0_d0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* tsi0_d1 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* tsi0_d2 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* tsi0_d3 */ + <3 RK_PB7 3 &pcfg_pull_none>, + /* tsi0_d4 */ + <3 RK_PA3 3 &pcfg_pull_none>, + /* tsi0_d5 */ + <3 RK_PA2 3 &pcfg_pull_none>, + /* tsi0_d6 */ + <3 RK_PA1 3 &pcfg_pull_none>, + /* tsi0_d7 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* tsi0_fail */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* tsi0_sync */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* tsi0_valid */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + tsi1 { + /omit-if-no-ref/ + tsi1_pins: tsi1-pins { + rockchip,pins = + /* tsi1_clkin */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* tsi1_d0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* tsi1_sync */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* tsi1_valid */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <4 RK_PC7 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <4 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <2 RK_PA0 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <2 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <4 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <4 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PC6 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PC5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1_ctsn: uart1-ctsn { + rockchip,pins = + /* uart1_ctsn */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1_rtsn: uart1-rtsn { + rockchip,pins = + /* uart1_rtsn */ + <4 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <3 RK_PA0 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <3 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <3 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <1 RK_PB0 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <1 RK_PB1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB0 2 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <4 RK_PB7 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <4 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4_xfer: uart4-xfer { + rockchip,pins = + /* uart4_rx */ + <2 RK_PA2 3 &pcfg_pull_up>, + /* uart4_tx */ + <2 RK_PA3 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PA2 2 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PA3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PA6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <1 RK_PD4 2 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <1 RK_PD7 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <3 RK_PC1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6_ctsn: uart6-ctsn { + rockchip,pins = + /* uart6_ctsn */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6_rtsn: uart6-rtsn { + rockchip,pins = + /* uart6_rtsn */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <1 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index d2cdb63d4a9d..9f6ccd9dd1f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -6,17 +6,299 @@ */ /dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> #include "rk3528.dtsi" / { model = "Radxa E20C"; compatible = "radxa,e20c", "rockchip,rk3528"; + aliases { + ethernet0 = &gmac1; + i2c1 = &i2c1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:1500000n8"; }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_key>; + + button-user { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "USER"; + linux,code = <BTN_1>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>; + + led-lan { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_LAN; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-sys { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-wan { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_WAN; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3>; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-keys { + user_key: user-key { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + lan_led_g: lan-led-g { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_g: sys-led-g { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_g: wan-led-g { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index e58faa985aa4..d1c72b52aa4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -4,8 +4,12 @@ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> */ +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rockchip,rk3528-cru.h> +#include <dt-bindings/reset/rockchip,rk3528-cru.h> / { compatible = "rockchip,rk3528"; @@ -15,14 +19,11 @@ #size-cells = <2>; aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; }; cpus { @@ -51,6 +52,7 @@ reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu1: cpu@1 { @@ -58,6 +60,7 @@ reg = <0x1>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu2: cpu@2 { @@ -65,6 +68,7 @@ reg = <0x2>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu3: cpu@3 { @@ -72,6 +76,90 @@ reg = <0x3>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3528-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff610000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffaf0000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ffb00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb00000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffb10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffb20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; }; }; @@ -80,6 +168,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -95,6 +195,13 @@ #clock-cells = <0>; }; + gmac0_clk: clock-gmac50m { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "gmac0"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; @@ -114,11 +221,231 @@ #interrupt-cells = <3>; }; + qos_crypto_a: qos@ff200000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200000 0x0 0x20>; + }; + + qos_crypto_p: qos@ff200080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200080 0x0 0x20>; + }; + + qos_dcf: qos@ff200100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200100 0x0 0x20>; + }; + + qos_dft2apb: qos@ff200200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200200 0x0 0x20>; + }; + + qos_dma2ddr: qos@ff200280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200280 0x0 0x20>; + }; + + qos_dmac: qos@ff200300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200300 0x0 0x20>; + }; + + qos_keyreader: qos@ff200380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200380 0x0 0x20>; + }; + + qos_cpu: qos@ff210000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210000 0x0 0x20>; + }; + + qos_debug: qos@ff210080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210080 0x0 0x20>; + }; + + qos_gpu_m0: qos@ff220000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220000 0x0 0x20>; + }; + + qos_gpu_m1: qos@ff220080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220080 0x0 0x20>; + }; + + qos_pmu_mcu: qos@ff240000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff240000 0x0 0x20>; + }; + + qos_rkvdec: qos@ff250000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff250000 0x0 0x20>; + }; + + qos_rkvenc: qos@ff260000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff260000 0x0 0x20>; + }; + + qos_gmac0: qos@ff270000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270000 0x0 0x20>; + }; + + qos_hdcp: qos@ff270080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270080 0x0 0x20>; + }; + + qos_jpegdec: qos@ff270100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270100 0x0 0x20>; + }; + + qos_rga2_m0ro: qos@ff270200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270200 0x0 0x20>; + }; + + qos_rga2_m0wo: qos@ff270280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270280 0x0 0x20>; + }; + + qos_sdmmc0: qos@ff270300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270300 0x0 0x20>; + }; + + qos_usb2host: qos@ff270380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270380 0x0 0x20>; + }; + + qos_vdpp: qos@ff270480 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270480 0x0 0x20>; + }; + + qos_vop: qos@ff270500 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270500 0x0 0x20>; + }; + + qos_emmc: qos@ff280000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280000 0x0 0x20>; + }; + + qos_fspi: qos@ff280080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280080 0x0 0x20>; + }; + + qos_gmac1: qos@ff280100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280100 0x0 0x20>; + }; + + qos_pcie: qos@ff280180 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280180 0x0 0x20>; + }; + + qos_sdio0: qos@ff280200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280200 0x0 0x20>; + }; + + qos_sdio1: qos@ff280280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280280 0x0 0x20>; + }; + + qos_tsp: qos@ff280300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280300 0x0 0x20>; + }; + + qos_usb3otg: qos@ff280380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280380 0x0 0x20>; + }; + + qos_vpu: qos@ff280400 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280400 0x0 0x20>; + }; + + vpu_grf: syscon@ff340000 { + compatible = "rockchip,rk3528-vpu-grf", "syscon"; + reg = <0x0 0xff340000 0x0 0x8000>; + }; + + vo_grf: syscon@ff360000 { + compatible = "rockchip,rk3528-vo-grf", "syscon"; + reg = <0x0 0xff360000 0x0 0x10000>; + }; + + cru: clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0x0 0xff4a0000 0x0 0x30000>; + assigned-clocks = + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>; + assigned-clock-rates = + <32768>, <1188000000>, + <1000000000>, <996000000>, + <408000000>, <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ioc_grf: syscon@ff540000 { + compatible = "rockchip,rk3528-ioc-grf", "syscon"; + reg = <0x0 0xff540000 0x0 0x40000>; + }; + uart0: serial@ff9f0000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f0000 0x0 0x100>; - clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 8>, <&dmac 9>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -127,7 +454,10 @@ uart1: serial@ff9f8000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f8000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 10>, <&dmac 11>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -136,7 +466,10 @@ uart2: serial@ffa00000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa00000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 12>, <&dmac 13>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -145,6 +478,10 @@ uart3: serial@ffa08000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa08000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 14>, <&dmac 15>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -153,7 +490,10 @@ uart4: serial@ffa10000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa10000 0x0 0x100>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 16>, <&dmac 17>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -162,7 +502,10 @@ uart5: serial@ffa18000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa18000 0x0 0x100>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 18>, <&dmac 19>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -171,7 +514,10 @@ uart6: serial@ffa20000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa20000 0x0 0x100>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 20>, <&dmac 21>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -180,10 +526,415 @@ uart7: serial@ffa28000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa28000 0x0 0x100>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac 22>, <&dmac 23>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; + + i2c0: i2c@ffa50000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa50000 0x0 0x1000>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ffa58000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa58000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa60000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa60000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa68000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa68000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa70000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa70000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa78000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa78000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ffa80000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ffa88000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa88000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@ffa90000 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90000 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@ffa90010 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90010 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@ffa90020 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90020 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ffa90030 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90030 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@ffa98000 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@ffa98010 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@ffa98020 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@ffa98030 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + saradc: adc@ffae0000 { + compatible = "rockchip,rk3528-saradc"; + reg = <0x0 0xffae0000 0x0 0x10000>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + gmac0: ethernet@ffbd0000 { + compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffbd0000 0x0 0x10000>; + clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, + <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, + <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; + clock-names = "stmmaceth", "clk_mac_ref", + "mac_clk_rx", "mac_clk_tx", + "pclk_mac", "aclk_mac"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + phy-handle = <&rmii0_phy>; + phy-mode = "rmii"; + resets = <&cru SRST_A_MAC_VO>; + reset-names = "stmmaceth"; + rockchip,grf = <&vo_grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + rmii0_phy: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x2>; + clocks = <&cru CLK_MACPHY>; + phy-is-integrated; + pinctrl-names = "default"; + pinctrl-0 = <&fephym0_led_link>, + <&fephym0_led_spd>; + resets = <&cru SRST_MACPHY>; + }; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + gmac1: ethernet@ffbe0000 { + compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffbe0000 0x0 0x10000>; + clocks = <&cru CLK_GMAC1_SRC_VPU>, + <&cru CLK_GMAC1_RMII_VPU>, + <&cru PCLK_MAC_VPU>, + <&cru ACLK_MAC_VPU>; + clock-names = "stmmaceth", + "clk_mac_ref", + "pclk_mac", + "aclk_mac"; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&cru SRST_A_MAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&vpu_grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sdhci: mmc@ffbf0000 { + compatible = "rockchip,rk3528-dwcmshc", + "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xffbf0000 0x0 0x10000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_SRC_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, + <200000000>; + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_strb>; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + sdio0: mmc@ffc10000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc10000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO0>, + <&cru CCLK_SRC_SDIO0>, + <&cru SCLK_SDIO0_DRV>, + <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; + resets = <&cru SRST_H_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio1: mmc@ffc20000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc20000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO1>, + <&cru CCLK_SRC_SDIO1>, + <&cru SCLK_SDIO1_DRV>, + <&cru SCLK_SDIO1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; + resets = <&cru SRST_H_SDIO1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC0>, + <&cru CCLK_SRC_SDMMC0>, + <&cru SCLK_SDMMC_DRV>, + <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + rockchip,default-sample-phase = <90>; + status = "disabled"; + }; + + dmac: dma-controller@ffd60000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xffd60000 0x0 0x4000>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; }; }; + +#include "rk3528-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts new file mode 100644 index 000000000000..6a84db154a7d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024-2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3562.dtsi" + +/ { + model = "Rockchip RK3562 EVB V20 Board"; + compatible = "rockchip,rk3562-evb2-v10", "rockchip,rk3562"; + + chosen: chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + linux,code = <KEY_VOLUMEUP>; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + linux,code = <KEY_VOLUMEDOWN>; + label = "volume down"; + press-threshold-microvolt = <414000>; + }; + + button-menu { + linux,code = <KEY_MENU>; + label = "menu"; + press-threshold-microvolt = <800000>; + }; + + button-back { + linux,code = <KEY_BACK>; + label = "back"; + press-threshold-microvolt = <1200000>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + work_led: led-0 { + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie20: regulator-vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + vcc3v3_clk: regulator-vcc3v3-clk { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: regulator-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc0 { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi new file mode 100644 index 000000000000..b311448d77a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -0,0 +1,2352 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + cam { + /omit-if-no-ref/ + camm0_clk0_out: camm0-clk0-out { + rockchip,pins = + /* camm0_clk0_out */ + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm0_clk1_out: camm0-clk1-out { + rockchip,pins = + /* camm0_clk1_out */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk0_out: camm1-clk0-out { + rockchip,pins = + /* camm1_clk0_out */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk1_out: camm1-clk1-out { + rockchip,pins = + /* camm1_clk1_out */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk2_out: cam-clk2-out { + rockchip,pins = + /* cam_clk2_out */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk3_out: cam-clk3-out { + rockchip,pins = + /* cam_clk3_out */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* can0_tx_m0 */ + <3 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <3 RK_PB7 6 &pcfg_pull_none>, + /* can0_tx_m1 */ + <3 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m2_pins: can0m2-pins { + rockchip,pins = + /* can0_rx_m2 */ + <0 RK_PC7 2 &pcfg_pull_none>, + /* can0_tx_m2 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* can1_tx_m0 */ + <1 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* can1_tx_m1 */ + <0 RK_PC0 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k_in: clk-32k-in { + rockchip,pins = + /* clk_32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + clk0 { + /omit-if-no-ref/ + clk0_32k_out: clk0-32k-out { + rockchip,pins = + /* clk0_32k_out */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + clk1 { + /omit-if-no-ref/ + clk1_32k_out: clk1-32k-out { + rockchip,pins = + /* clk1_32k_out */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + dsm { + /omit-if-no-ref/ + dsm_pins: dsm-pins { + rockchip,pins = + /* dsm_aud_ln */ + <1 RK_PB4 5 &pcfg_pull_none>, + /* dsm_aud_lp */ + <1 RK_PB3 5 &pcfg_pull_none>, + /* dsm_aud_rn */ + <1 RK_PB6 6 &pcfg_pull_none>, + /* dsm_aud_rp */ + <1 RK_PB5 6 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + ethm0_pins: ethm0-pins { + rockchip,pins = + /* eth_clk_25m_out_m0 */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ethm1_pins: ethm1-pins { + rockchip,pins = + /* eth_clk_25m_out_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PB1 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PA0 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PB5 5 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <3 RK_PD3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <3 RK_PA0 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <3 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <4 RK_PA5 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <4 RK_PA6 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PB6 5 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PB7 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC2 1 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PC7 4 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD0 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PA2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PA3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi0: i2s0m0-sdi0 { + rockchip,pins = + /* i2s0_sdi0_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi1: i2s0m0-sdi1 { + rockchip,pins = + /* i2s0_sdi1_m0 */ + <3 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi2: i2s0m0-sdi2 { + rockchip,pins = + /* i2s0_sdi2_m0 */ + <3 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi3: i2s0m0-sdi3 { + rockchip,pins = + /* i2s0_sdi3_m0 */ + <3 RK_PA6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo0: i2s0m0-sdo0 { + rockchip,pins = + /* i2s0_sdo0_m0 */ + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo1: i2s0m0-sdo1 { + rockchip,pins = + /* i2s0_sdo1_m0 */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo2: i2s0m0-sdo2 { + rockchip,pins = + /* i2s0_sdo2_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo3: i2s0m0-sdo3 { + rockchip,pins = + /* i2s0_sdo3_m0 */ + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PC4 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PC6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PC5 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi0: i2s0m1-sdi0 { + rockchip,pins = + /* i2s0_sdi0_m1 */ + <1 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi1: i2s0m1-sdi1 { + rockchip,pins = + /* i2s0_sdi1_m1 */ + <1 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi2: i2s0m1-sdi2 { + rockchip,pins = + /* i2s0_sdi2_m1 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi3: i2s0m1-sdi3 { + rockchip,pins = + /* i2s0_sdi3_m1 */ + <1 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo0: i2s0m1-sdo0 { + rockchip,pins = + /* i2s0_sdo0_m1 */ + <1 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo1: i2s0m1-sdo1 { + rockchip,pins = + /* i2s0_sdo1_m1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo2: i2s0m1-sdo2 { + rockchip,pins = + /* i2s0_sdo2_m1 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo3: i2s0m1-sdo3 { + rockchip,pins = + /* i2s0_sdo3_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1_lrck_m0 */ + <3 RK_PC6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1_mclk_m0 */ + <3 RK_PC4 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1_sclk_m0 */ + <3 RK_PC5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1_sdi0_m0 */ + <3 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1_sdi1_m0 */ + <3 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1_sdi2_m0 */ + <3 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1_sdi3_m0 */ + <3 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1_sdo0_m0 */ + <3 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1_sdo1_m0 */ + <4 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1_sdo2_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1_sdo3_m0 */ + <4 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1_lrck_m1 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1_mclk_m1 */ + <3 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1_sclk_m1 */ + <3 RK_PB3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1_sdi0_m1 */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1_sdi1_m1 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1_sdi2_m1 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1_sdi3_m1 */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1_sdo0_m1 */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1_sdo1_m1 */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1_sdo2_m1 */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1_sdo3_m1 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2_lrck_m0 */ + <1 RK_PD6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2_mclk_m0 */ + <2 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2_sclk_m0 */ + <1 RK_PD5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2_sdi_m0 */ + <2 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2_sdo_m0 */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2_lrck_m1 */ + <4 RK_PA1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2_mclk_m1 */ + <3 RK_PD6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2_sclk_m1 */ + <4 RK_PB1 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2_sdi_m1 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2_sdo_m1 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flash_trigin */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* isp_flash_trigout */ + <3 RK_PC3 2 &pcfg_pull_none>, + /* isp_prelight_trigout */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_mcu_tck_m0 */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m0 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_mcu_tck_m1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m1 */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqn_m0 */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* pcie20_perstn_m0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* pcie20_waken_m0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqn_m1 */ + <3 RK_PA6 4 &pcfg_pull_none>, + /* pcie20_perstn_m1 */ + <3 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_waken_m1 */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk0: pdmm0-clk0 { + rockchip,pins = + /* pdm_clk0_m0 */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdm_clk1_m0 */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdm_sdi0_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdm_sdi1_m0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdm_sdi2_m0 */ + <3 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdm_sdi3_m0 */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk0: pdmm1-clk0 { + rockchip,pins = + /* pdm_clk0_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdm_clk1_m1 */ + <4 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdm_sdi0_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdm_sdi1_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdm_sdi2_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdm_sdi3_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA3 0 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <0 RK_PA2 0 &pcfg_output_low>; + }; + + /omit-if-no-ref/ + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PC3 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PC7 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <0 RK_PA7 1 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <1 RK_PD0 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PB7 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PD1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PC2 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <1 RK_PD2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC1 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PD3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <0 RK_PC0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PD4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PC1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PA5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PC2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <1 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <1 RK_PC3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_m0 */ + <1 RK_PB6 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_m1 */ + <1 RK_PC4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <4 RK_PA1 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <3 RK_PB4 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <3 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <1 RK_PD7 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_m0 */ + <3 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_m1 */ + <2 RK_PA0 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + ref_pins: ref-pins { + rockchip,pins = + /* ref_clk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmiim0_miim: rgmiim0-miim { + rockchip,pins = + /* rgmii_mdc_m0 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* rgmii_mdio_m0 */ + <4 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_er: rgmiim0-rx_er { + rockchip,pins = + /* rgmii_rxer_m0 */ + <4 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_bus2: rgmiim0-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0_m0 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m0 */ + <4 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_tx_bus2: rgmiim0-tx_bus2 { + rockchip,pins = + /* rgmii_txd0_m0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_txd1_m0 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_txen_m0 */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_clk: rgmiim0-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk_m0 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* rgmii_txclk_m0 */ + <3 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_bus: rgmiim0-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2_m0 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* rgmii_txd2_m0 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_txd3_m0 */ + <3 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_clk: rgmiim0-clk { + rockchip,pins = + /* rgmiim0_clk */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins = + /* rgmii_mdc_m1 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_er: rgmiim1-rx_er { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_bus2: rgmiim1-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0_m1 */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_tx_bus2: rgmiim1-tx_bus2 { + rockchip,pins = + /* rgmii_txd0_m1 */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* rgmii_txd1_m1 */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* rgmii_txen_m1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_clk: rgmiim1-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_bus: rgmiim1-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2_m1 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* rgmii_txd2_m1 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_txd3_m1 */ + <1 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_clk: rgmiim1-clk { + rockchip,pins = + /* rgmiim1_clk */ + <1 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + rmii { + /omit-if-no-ref/ + rmii_pins: rmii-pins { + rockchip,pins = + /* rmii_clk */ + <1 RK_PD5 5 &pcfg_pull_none>, + /* rmii_mdc */ + <1 RK_PC7 5 &pcfg_pull_none>, + /* rmii_mdio */ + <1 RK_PD0 5 &pcfg_pull_none>, + /* rmii_rxd0 */ + <1 RK_PD4 5 &pcfg_pull_none>, + /* rmii_rxd1 */ + <1 RK_PD7 6 &pcfg_pull_none>, + /* rmii_rxdv_crs */ + <1 RK_PD6 5 &pcfg_pull_none>, + /* rmii_rxer */ + <2 RK_PA0 6 &pcfg_pull_none>, + /* rmii_txd0 */ + <1 RK_PD1 5 &pcfg_pull_none>, + /* rmii_txd1 */ + <1 RK_PD2 5 &pcfg_pull_none>, + /* rmii_txen */ + <1 RK_PD3 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_detn */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_detn */ + <1 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <0 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC3 3 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m0 */ + <0 RK_PC5 3 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m0 */ + <0 RK_PC4 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m0_csn0: spi0m0-csn0 { + rockchip,pins = + /* spi0m0_csn0 */ + <0 RK_PC2 3 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m0_csn1: spi0m0-csn1 { + rockchip,pins = + /* spi0m0_csn1 */ + <0 RK_PB7 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <3 RK_PB5 4 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m1 */ + <3 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m1 */ + <3 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_csn0: spi0m1-csn0 { + rockchip,pins = + /* spi0m1_csn0 */ + <3 RK_PB7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m1_csn1: spi0m1-csn1 { + rockchip,pins = + /* spi0m1_csn1 */ + <3 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <3 RK_PD6 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m0 */ + <4 RK_PA3 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m0 */ + <4 RK_PA2 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m0_csn0: spi1m0-csn0 { + rockchip,pins = + /* spi1m0_csn0 */ + <3 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m0_csn1: spi1m0-csn1 { + rockchip,pins = + /* spi1m0_csn1 */ + <4 RK_PA0 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <1 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m1 */ + <1 RK_PB4 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m1 */ + <1 RK_PB3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins = + /* spi1m1_csn0 */ + <1 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m1_csn1: spi1m1-csn1 { + rockchip,pins = + /* spi1m1_csn1 */ + <1 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <4 RK_PB6 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m0 */ + <3 RK_PD2 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m0 */ + <3 RK_PD3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m0_csn0: spi2m0-csn0 { + rockchip,pins = + /* spi2m0_csn0 */ + <4 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m0_csn1: spi2m0-csn1 { + rockchip,pins = + /* spi2m0_csn1 */ + <4 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <2 RK_PA1 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m1 */ + <2 RK_PA0 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m1 */ + <1 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_csn0: spi2m1-csn0 { + rockchip,pins = + /* spi2m1_csn0 */ + <1 RK_PD6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m1_csn1: spi2m1-csn1 { + rockchip,pins = + /* spi2m1_csn1 */ + <1 RK_PD5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_pins: tsadcm0-pins { + rockchip,pins = + /* tsadc_shut_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_pins: tsadcm1-pins { + rockchip,pins = + /* tsadc_shut_m1 */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <1 RK_PD1 1 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <1 RK_PD2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <1 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PA6 3 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PA5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PC1 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PC0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA1 2 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB5 6 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB4 6 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <4 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PC0 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB7 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_ctsn: uart3m1-ctsn { + rockchip,pins = + /* uart3m1_ctsn */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m1_rtsn: uart3m1-rtsn { + rockchip,pins = + /* uart3m1_rtsn */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PD1 3 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PD0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <3 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <1 RK_PD5 3 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <1 RK_PD6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_ctsn: uart4m1-ctsn { + rockchip,pins = + /* uart4m1_ctsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m1_rtsn: uart4m1-rtsn { + rockchip,pins = + /* uart4m1_rtsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PB7 3 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PA7 5 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PA6 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <3 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <0 RK_PC7 1 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <0 RK_PC6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <4 RK_PB0 5 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <4 RK_PA7 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PC7 3 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PC4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 3 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB4 3 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <3 RK_PB3 3 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <3 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PD5 3 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <4 RK_PB3 3 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <4 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <3 RK_PC3 3 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <3 RK_PC2 3 &pcfg_pull_up>; + }; + }; + + vo { + /omit-if-no-ref/ + vo_pins: vo-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d0 */ + <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d1 */ + <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d8 */ + <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d9 */ + <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d16 */ + <4 RK_PB0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d17 */ + <4 RK_PB1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + vo { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m0: rgb3x8-pins-m0 { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m1: rgb3x8-pins-m1 { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb565_pins: rgb565-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb666_pins: rgb666-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi new file mode 100644 index 000000000000..def504ffa326 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -0,0 +1,1185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rockchip,rk3562-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/reset/rockchip,rk3562-cru.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3562"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + }; + + xin32k: clock-xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: clock-xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <925000 925000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1000000 1000000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1037500 1037500 1150000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1125000 1125000 1150000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1150000 1150000 1150000>; + clock-latency-ns = <40000>; + }; + + }; + + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000 900000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3562-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff620000 0x0 0x100>; + clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff630000 0x0 0x100>; + clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffac0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffac0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffad0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffad0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pcie2x1: pcie@fe000000 { + compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xff>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power 15>; + ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gic: interrupt-controller@fe901000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfe901000 0 0x1000>, + <0x0 0xfe902000 0 0x2000>, + <0x0 0xfe904000 0 0x2000>, + <0x0 0xfe906000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + qos_dma2ddr: qos@fee03800 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee03800 0x0 0x20>; + }; + + qos_mcu: qos@fee10000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee10000 0x0 0x20>; + }; + + qos_dft_apb: qos@fee10100 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee10100 0x0 0x20>; + }; + + qos_gmac: qos@fee10200 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee10200 0x0 0x20>; + }; + + qos_mac100: qos@fee10300 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee10300 0x0 0x20>; + }; + + qos_dcf: qos@fee10400 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee10400 0x0 0x20>; + }; + + qos_cpu: qos@fee20000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee20000 0x0 0x20>; + }; + + qos_gpu: qos@fee30000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee30000 0x0 0x20>; + }; + + qos_npu: qos@fee40000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee40000 0x0 0x20>; + }; + + qos_rkvdec: qos@fee50000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee50000 0x0 0x20>; + }; + + qos_vepu: qos@fee60000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee60000 0x0 0x20>; + }; + + qos_isp: qos@fee70000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee70000 0x0 0x20>; + }; + + qos_vicap: qos@fee70100 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee70100 0x0 0x20>; + }; + + qos_vop: qos@fee80000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee80000 0x0 0x20>; + }; + + qos_jpeg: qos@fee90000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee90000 0x0 0x20>; + }; + + qos_rga_rd: qos@fee90100 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee90100 0x0 0x20>; + }; + + qos_rga_wr: qos@fee90200 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfee90200 0x0 0x20>; + }; + + qos_pcie: qos@feea0000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeea0000 0x0 0x20>; + }; + + qos_usb3: qos@feea0100 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeea0100 0x0 0x20>; + }; + + qos_crypto_apb: qos@feeb0000 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0000 0x0 0x20>; + }; + + qos_crypto: qos@feeb0100 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0100 0x0 0x20>; + }; + + qos_dmac: qos@feeb0200 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0200 0x0 0x20>; + }; + + qos_emmc: qos@feeb0300 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0300 0x0 0x20>; + }; + + qos_fspi: qos@feeb0400 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0400 0x0 0x20>; + }; + + qos_rkdma: qos@feeb0500 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0500 0x0 0x20>; + }; + + qos_sdmmc0: qos@feeb0600 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0600 0x0 0x20>; + }; + + qos_sdmmc1: qos@feeb0700 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0700 0x0 0x20>; + }; + + qos_usb2: qos@feeb0800 { + compatible = "rockchip,rk3562-qos", "syscon"; + reg = <0x0 0xfeeb0800 0x0 0x20>; + }; + + pmu_grf: syscon@ff010000 { + compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff010000 0x0 0x10000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x220>; + mode-normal = <BOOT_NORMAL>; + mode-loader = <BOOT_BL_DOWNLOAD>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + }; + }; + + sys_grf: syscon@ff030000 { + compatible = "rockchip,rk3562-sys-grf", "syscon"; + reg = <0x0 0xff030000 0x0 0x10000>; + }; + + peri_grf: syscon@ff040000 { + compatible = "rockchip,rk3562-peri-grf", "syscon"; + reg = <0x0 0xff040000 0x0 0x10000>; + }; + + ioc_grf: syscon@ff060000 { + compatible = "rockchip,rk3562-ioc-grf", "syscon"; + reg = <0x0 0xff060000 0x0 0x30000>; + }; + + usbphy_grf: syscon@ff090000 { + compatible = "rockchip,rk3562-usbphy-grf", "syscon"; + reg = <0x0 0xff090000 0x0 0x8000>; + }; + + pipephy_grf: syscon@ff098000 { + compatible = "rockchip,rk3562-pipephy-grf", "syscon"; + reg = <0x0 0xff098000 0x0 0x8000>; + }; + + cru: clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0x0 0xff100000 0x0 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_HPLL>; + assigned-clock-rates = <1188000000>, <1000000000>, + <983040000>; + }; + + i2c0: i2c@ff200000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff200000 0x0 0x1000>; + clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@ff210000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff210000 0x0 0x100>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi0: spi@ff220000 { + compatible = "rockchip,rk3562-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff220000 0x0 0x1000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@ff230000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230000 0x0 0x10>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@ff230010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230010 0x0 0x10>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@ff230020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230020 0x0 0x10>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ff230030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230030 0x0 0x10>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@ff258000 { + compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff258000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3562-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@8 { + reg = <8>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + + power-domain@7 { + reg = <7>; + pm_qos = <&qos_npu>; + #power-domain-cells = <0>; + }; + + power-domain@11 { + reg = <11>; + pm_qos = <&qos_rkvdec>; + #power-domain-cells = <0>; + }; + + power-domain@12 { + reg = <12>; + pm_qos = <&qos_isp>, + <&qos_vicap>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@10 { + reg = <10>; + pm_qos = <&qos_vepu>; + #power-domain-cells = <0>; + }; + }; + + power-domain@13 { + reg = <13>; + pm_qos = <&qos_vop>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@14 { + reg = <14>; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_jpeg>; + #power-domain-cells = <0>; + }; + }; + + power-domain@15 { + reg = <15>; + pm_qos = <&qos_pcie>, + <&qos_usb3>; + #power-domain-cells = <0>; + }; + }; + }; + + gpu: gpu@ff320000 { + compatible = "rockchip,rk3562-mali", "arm,mali-bifrost"; + reg = <0x0 0xff320000 0x0 0x4000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>, + <&cru ACLK_GPU_PRE>; + clock-names = "clk_gpu", "clk_gpu_brg", "aclk_gpu"; + dynamic-power-coefficient = <820>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power 8>; + #cooling-cells = <2>; + status = "disabled"; + }; + + spi1: spi@ff640000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff640000 0x0 0x1000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff650000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff650000 0x0 0x1000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 17>, <&dmac 16>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@ff670000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff670000 0x0 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff680000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff680000 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff690000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff6a0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6a0000 0x0 0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff6b0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6b0000 0x0 0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart6: serial@ff6c0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6c0000 0x0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart7: serial@ff6d0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6d0000 0x0 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart8: serial@ff6e0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6e0000 0x0 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart9: serial@ff6f0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6f0000 0x0 0x100>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pwm4: pwm@ff700000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700000 0x0 0x10>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm4m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@ff700010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700010 0x0 0x10>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@ff700020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700020 0x0 0x10>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm6m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@ff700030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700030 0x0 0x10>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@ff710000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710000 0x0 0x10>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm8m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@ff710010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710010 0x0 0x10>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm9m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@ff710020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710020 0x0 0x10>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm10m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@ff710030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710030 0x0 0x10>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm11m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@ff720000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720000 0x0 0x10>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@ff720010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720010 0x0 0x10>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm13m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@ff720020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720020 0x0 0x10>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@ff720030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720030 0x0 0x10>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + saradc0: adc@ff730000 { + compatible = "rockchip,rk3562-saradc"; + reg = <0x0 0xff730000 0x0 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + combphy: phy@ff750000 { + compatible = "rockchip,rk3562-naneng-combphy"; + reg = <0x0 0xff750000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, + <&cru PCLK_PHP>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_PIPEPHY_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&peri_grf>; + rockchip,pipe-phy-grf = <&pipephy_grf>; + status = "disabled"; + }; + + sfc: spi@ff860000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff860000 0x0 0x10000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhci: mmc@ff870000 { + compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xff870000 0x0 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdmmc0: mmc@ff880000 { + compatible = "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff880000 0x0 0x10000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@ff890000 { + compatible = "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff890000 0x0 0x10000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + resets = <&cru SRST_H_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + dmac: dma-controller@ff990000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff990000 0x0 0x4000>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + }; + + i2c1: i2c@ffa00000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa00000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa10000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa10000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa20000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa20000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa30000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa30000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa40000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa40000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + saradc1: adc@ffaa0000 { + compatible = "rockchip,rk3562-saradc"; + reg = <0x0 0xffaa0000 0x0 0x100>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC_VCCIO156>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; +}; + +#include "rk3562-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi index a48351471764..e7ba477e75f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -775,7 +775,7 @@ rockchip,default-sample-phase = <90>; status = "okay"; - sdio-wifi@1 { + wifi@1 { compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio2>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts index 7d4680933823..decc6deeef4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts @@ -19,9 +19,9 @@ aliases { ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdmmc1; - mmc2 = &sdhci; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; }; chosen: chosen { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts b/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts index 61dd71c259aa..ddf84c2a19cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts @@ -512,7 +512,6 @@ &sdmmc0 { max-frequency = <150000000>; - supports-sd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 2d3ae1544822..3613661417b2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -9,6 +9,8 @@ #include "rk3566.dtsi" / { + chassis-type = "tablet"; + aliases { mmc0 = &sdhci; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi index 26cf765a7297..3473b1eef5cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi @@ -867,6 +867,7 @@ spi-max-frequency = <100000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 98e75df8b158..3c127c5c2607 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -265,8 +265,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-supply = <&vcc_3v3>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts index 24928a129446..f8cf03380636 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -173,8 +173,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; @@ -644,6 +648,7 @@ spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts index 53e71528e4c4..6224d72813e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -636,6 +636,7 @@ spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index b6ad8328c7eb..3b31f0dd8f3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -20,33 +20,43 @@ gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&sys_led_pin>, <&wan_led_pin>; led-lan1 { color = <LED_COLOR_ID_GREEN>; + default-state = "off"; function = LED_FUNCTION_LAN; function-enumerator = <1>; gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + label = "LAN-1"; + linux,default-trigger = "netdev"; }; led-lan2 { color = <LED_COLOR_ID_GREEN>; + default-state = "off"; function = LED_FUNCTION_LAN; function-enumerator = <2>; gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + label = "LAN-2"; + linux,default-trigger = "netdev"; }; - power_led: led-power { + power_led: led-sys { color = <LED_COLOR_ID_RED>; function = LED_FUNCTION_POWER; - linux,default-trigger = "heartbeat"; gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + label = "SYS"; + linux,default-trigger = "heartbeat"; }; led-wan { color = <LED_COLOR_ID_GREEN>; + default-state = "off"; function = LED_FUNCTION_WAN; gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "WAN"; + linux,default-trigger = "netdev"; }; }; }; @@ -58,6 +68,7 @@ clock_in_out = "output"; phy-handle = <&rgmii_phy0>; phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 @@ -125,7 +136,7 @@ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; - power_led_pin: power-led-pin { + sys_led_pin: sys-led-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi index 00c479aa1871..a28b4af10d13 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi @@ -486,9 +486,12 @@ &sdhci { bus-width = <8>; max-frequency = <200000000>; + mmc-hs200-1_8v; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts new file mode 100644 index 000000000000..58c1052ba8ef --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Ariaboard Photonicat"; + compatible = "ariaboard,photonicat", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <6800000>; + energy-full-design-microwatt-hours = <25000000>; + voltage-max-design-microvolt = <4200000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = <4100000 100>, <4040000 90>, + <3980000 80>, <3920000 70>, + <3870000 60>, <3820000 50>, + <3790000 40>, <3770000 30>, + <3740000 20>, <3680000 10>, + <3450000 0>; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi_con: hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* actually fed by vcc_syson, dependent + * on pi6c clock generator + */ + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c: regulator-vcc3v3-pi6c { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pi6c"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v3_sd: regulator-vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwren>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v4_rf: regulator-vcc3v4-rf { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rf_pwr_en>; + regulator-name = "vcc3v4_rf"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + vin-supply = <&vccin_5v>; + }; + + vcc5v0_usb30_otg0: regulator-vcc5v0-usb30-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb30_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vccin_5v: regulator-vccin-5v { + compatible = "regulator-fixed"; + regulator-name = "vccin_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sysin: regulator-vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vcc_syson: regulator-vcc-syson { + compatible = "regulator-fixed"; + regulator-name = "vcc_syson"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcca_1v8: regulator-vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdda_0v9: regulator-vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_gpu: regulator-vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + rfkill-modem { + compatible = "rfkill-gpio"; + label = "M.2 USB Modem"; + radio-type = "wwan"; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h &clk32k_out1>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +/* Motorcomm YT8521SC LAN port (require SGMII) */ +&gmac0 { + status = "disabled"; +}; + +/* Motorcomm YT8521SC WAN port */ +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_syson>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +/* M.2 E-Key for PCIe WLAN */ +&pcie3x2 { + max-link-speed = <1>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + rf_pwr_en: rf-pwr-en { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* Micro SD card slot */ +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 WiFi */ +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 Bluetooth */ +&uart1 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&pmucru CLK_RTC_32K>; + enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>; + vddio-supply = <&vcc_1v8>; + }; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +&uart3 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* Onboard power management MCU */ +&uart4 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* M.2 E-Key for USB Bluetooth */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-A Port */ +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* M.2 B-Key for USB Modem WWAN */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc3v4_rf>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&xin32k { + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_out1>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 7bd32d230ad2..6ae4316761c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -481,9 +481,14 @@ }; &mdio0 { - rgmii_phy0: ethernet-phy@0 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; }; }; @@ -556,6 +561,12 @@ }; &pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + keys { copy_button_pin: copy-button-pin { rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; @@ -619,6 +630,8 @@ bus-width = <8>; max-frequency = <200000000>; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index ac79140a9ecd..44cfdfeed668 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -778,20 +778,6 @@ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; uart-has-rtscts; status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; }; &uart2 { diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 695cccbdab0f..e719a3df126c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -152,7 +152,7 @@ compatible = "rockchip,rk3568-pcie"; #address-cells = <3>; #size-cells = <2>; - bus-range = <0x0 0xf>; + bus-range = <0x10 0x1f>; clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, <&cru CLK_PCIE30X1_AUX_NDFT>; @@ -175,7 +175,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <3>; - msi-map = <0x0 &gic 0x1000 0x1000>; + msi-map = <0x1000 &its 0x1000 0x1000>; num-lanes = <1>; phys = <&pcie30phy>; phy-names = "pcie-phy"; @@ -205,7 +205,7 @@ compatible = "rockchip,rk3568-pcie"; #address-cells = <3>; #size-cells = <2>; - bus-range = <0x0 0xf>; + bus-range = <0x20 0x2f>; clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, <&cru CLK_PCIE30X2_AUX_NDFT>; @@ -228,7 +228,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <3>; - msi-map = <0x0 &gic 0x2000 0x1000>; + msi-map = <0x2000 &its 0x2000 0x1000>; num-lanes = <2>; phys = <&pcie30phy>; phy-names = "pcie-phy"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index e55390629114..fd2214b6fad4 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -174,6 +174,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, @@ -199,19 +211,6 @@ #clock-cells = <0>; }; - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - sata1: sata@fc400000 { compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; reg = <0 0xfc400000 0 0x1000>; @@ -284,6 +283,18 @@ mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + its: msi-controller@fd440000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfd440000 0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; }; usb_host0_ehci: usb@fd800000 { @@ -957,7 +968,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; + msi-map = <0x0 &its 0x0 0x1000>; num-lanes = <1>; phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; @@ -1032,6 +1043,11 @@ status = "disabled"; }; + /* + * Testing showed that the HWRNG found in RK3566 produces unacceptably + * low quality of random data, so the HWRNG isn't enabled for all RK356x + * SoC variants despite its presence. + */ rng: rng@fe388000 { compatible = "rockchip,rk3568-rng"; reg = <0x0 0xfe388000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 7c7331936a7f..b09e789c75c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -10,6 +10,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include <dt-bindings/usb/pd.h> #include "rk3576.dtsi" @@ -26,6 +27,17 @@ stdout-path = "serial0:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -44,6 +56,34 @@ }; }; + es8388_sound: es8388-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "On-board Analog ES8388"; + simple-audio-card,widgets = "Microphone", "Headphone Mic", + "Microphone", "Mic Pads", + "Headphone", "Headphone", + "Line Out", "Line Out"; + simple-audio-card,routing = "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Line Out", "LOUT2", + "Line Out", "ROUT2", + "RINPUT1", "Headphone Mic", + "LINPUT2", "Mic Pads", + "RINPUT2", "Mic Pads"; + simple-audio-card,pin-switches = "Headphone", "Line Out"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + vcc_12v0_dcin: regulator-vcc-12v0-dcin { compatible = "regulator-fixed"; regulator-name = "vcc_12v0_dcin"; @@ -105,6 +145,8 @@ vcc_3v3_pcie: regulator-vcc-3v3-pcie { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc_3v3_pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -165,6 +207,10 @@ }; }; +&combphy0_ps { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -182,8 +228,7 @@ ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>; phy-handle = <&rgmii_phy0>; status = "okay"; @@ -214,6 +259,30 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -579,7 +648,7 @@ reg = <0x51>; clock-output-names = "hym8563"; interrupt-parent = <&gpio0>; - interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&hym8563_int>; wakeup-source; @@ -587,6 +656,25 @@ }; }; +&i2c3 { + status = "okay"; + + es8388: audio-codec@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcc_3v3_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcc_3v3_s0>; + assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + }; +}; + &mdio0 { rgmii_phy0: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -603,6 +691,14 @@ }; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie>; + status = "okay"; +}; + &pinctrl { headphone { hp_det: hp-det { @@ -624,6 +720,28 @@ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + pcie_reset: pcie-reset { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; + status = "okay"; +}; + +&sai6 { + status = "okay"; }; &sdhci { @@ -656,3 +774,18 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 782ca000a644..0902d694cef4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -10,6 +10,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3576.dtsi" / { @@ -57,6 +58,17 @@ }; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -116,7 +128,7 @@ vin-supply = <&vcc_3v3_s0>; }; - vcc3v3_pcie0: regulator-vcc3v3-pcie0 { + vcc3v3_pcie1: regulator-vcc3v3-pcie1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie1"; regulator-min-microvolt = <3300000>; @@ -270,6 +282,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -659,6 +691,17 @@ }; }; +&pcie1 { + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie1>; + + /* + * Disable usb_drd1_dwc3 if enabling pcie1 and set Dial_Switch_1 + * to low state according to the schematic of page 17. + */ + status = "disabled"; +}; + &pinctrl { usb { usb_host_pwren: usb-host-pwren { @@ -715,6 +758,10 @@ status = "okay"; }; +&ufshc { + status = "okay"; +}; + &usbdp_phy { rockchip,dp-lane-mux = <2 3>; status = "okay"; @@ -729,3 +776,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts new file mode 100644 index 000000000000..d4e437ea6cd8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -0,0 +1,783 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Firefly Technology Co. Ltd + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3576.dtsi" + +/ { + model = "Firefly ROC-RK3576-PC"; + compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <17000>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <17000>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren_h>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v0_device_s0: regulator-vcc5v0-device-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5vd_en>; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_host_pwren_h>; + regulator-name = "vcc5v0_host1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + phy-handle = <&rgmii_phy0>; + tx_delay = <0x21>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + /* Reset time is 20ms, 100ms for rtl8211f */ + reset-delay-us = <20000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <100000>; + }; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys_s5>; + vcc2-supply = <&vcc5v0_sys_s5>; + vcc3-supply = <&vcc5v0_sys_s5>; + vcc4-supply = <&vcc5v0_sys_s5>; + vcc5-supply = <&vcc5v0_sys_s5>; + vcc6-supply = <&vcc5v0_sys_s5>; + vcc7-supply = <&vcc5v0_sys_s5>; + vcc8-supply = <&vcc5v0_sys_s5>; + vcc9-supply = <&vcc5v0_sys_s5>; + vcc10-supply = <&vcc5v0_sys_s5>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys_s5>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys_s5>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + /* hnyetek,husb311 typec-portc@4e */ + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc5vd_en: vcc5vd-en { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + hub_reset_h: hub-reset-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb3_host_pwren_h: usb3-host-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren_h: usb-otg0-pwren-h { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int_l: usbc0-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + watchdog { + wd_en: wd-en { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>; + status = "okay"; +}; + +/* On the extension pin header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m3_xfer>; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts new file mode 100644 index 000000000000..6756403111e7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3576.dtsi" + +/ { + model = "Radxa ROCK 4D"; + compatible = "radxa,rock-4d", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g &led_rgb_r>; + + power-led { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + user-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_12v0_dcin: regulator-vcc-12v0-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc_12v0_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc_1v2_ufs_vccq_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_ufs_vccq2_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_pcie"; + startup-delay-us = <5000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_rtc_s5"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_ufs_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_device"; + vin-supply = <&vcc_12v0_dcin>; + }; + + vcc_5v0_host: regulator-vcc-5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc_5v0_device>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_sys"; + vin-supply = <&vcc_12v0_dcin>; + }; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_rgb_g: led-green-en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-red-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren: pcie-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + + +&sfc0 { + pinctrl-names = "default"; + pinctrl-0 = <&fspi0_pins &fspi0_csn0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8_s3>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 4dde954043ef..1086482f0479 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -111,7 +111,7 @@ reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <120>; @@ -124,7 +124,7 @@ reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -135,7 +135,7 @@ reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -146,7 +146,7 @@ reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -157,7 +157,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <320>; @@ -170,7 +170,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -181,7 +181,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -192,7 +192,7 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -393,6 +393,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -408,6 +413,90 @@ }; }; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai6>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3576-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@27320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x27320000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2ae10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2ae20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2ae30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae30000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@2ae40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae40000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + pmu_a53: pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -445,6 +534,114 @@ #size-cells = <2>; ranges; + pcie0: pcie@22000000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_PHP>; + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie1: pcie@22400000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy1_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_SUBPHP>; + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; + }; + }; + usb_drd0_dwc3: usb@23000000 { compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; reg = <0x0 0x23000000 0x0 0x400000>; @@ -620,6 +817,11 @@ }; }; + hdptxphy_grf: syscon@26032000 { + compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; + reg = <0x0 0x26032000 0x0 0x100>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -922,7 +1124,7 @@ gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; reg = <0x0 0x27800000 0x0 0x200000>; - assigned-clocks = <&scmi_clk CLK_GPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; clock-names = "core"; @@ -937,6 +1139,196 @@ status = "disabled"; }; + vop: vop@27d00000 { + compatible = "rockchip,rk3576-vop"; + reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", + "vp0", + "vp1", + "vp2"; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VP0>, + <&cru DCLK_VP1>, + <&cru DCLK_VP2>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3576_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; + }; + + vop_mmu: iommu@27d07e00 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3576_PD_VOP>; + status = "disabled"; + }; + + sai5: sai@27d40000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27d40000 0x0 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 3>; + dma-names = "rx"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; + reset-names = "m", "h"; + rockchip,sai-rx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI5"; + status = "disabled"; + }; + + sai6: sai@27d50000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27d50000 0x0 0x1000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 4>, <&dmac2 5>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; + reset-names = "m", "h"; + rockchip,sai-rx-route = <0 1 2 3>; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI6"; + status = "disabled"; + }; + + hdmi: hdmi@27da0000 { + compatible = "rockchip,rk3576-dw-hdmi-qp"; + reg = <0x0 0x27da0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_SAI6_8CH>, + <&cru CLK_HDMITXHDP>, + <&cru HCLK_VO0_ROOT>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; + reset-names = "ref", "hdp"; + rockchip,grf = <&ioc_grf>; + rockchip,vo-grf = <&vo0_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + sai7: sai@27ed0000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27ed0000 0x0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 19>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; + reset-names = "m", "h"; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI7"; + status = "disabled"; + }; + + sai8: sai@27ee0000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27ee0000 0x0 0x1000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 7>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; + reset-names = "m", "h"; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI8"; + status = "disabled"; + }; + + sai9: sai@27ef0000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27ef0000 0x0 0x1000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 26>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; + reset-names = "m", "h"; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI9"; + status = "disabled"; + }; + qos_hdcp1: qos@27f02000 { compatible = "rockchip,rk3576-qos", "syscon"; reg = <0x0 0x27f02000 0x0 0x20>; @@ -1221,6 +1613,72 @@ }; }; + sata0: sata@2a240000 { + compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; + reg = <0x0 0x2a240000 0x0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_SUBPHP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + dma-coherent; + status = "disabled"; + }; + + sata1: sata@2a250000 { + compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; + reg = <0x0 0x2a250000 0x0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_SUBPHP>; + phys = <&combphy1_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + dma-coherent; + status = "disabled"; + }; + + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + assigned-clocks = <&cru CLK_REF_OSC_MPHY>; + assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_USB>; + pinctrl-0 = <&ufs_refclk>; + pinctrl-names = "default"; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + sfc1: spi@2a300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a300000 0x0 0x4000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + power-domains = <&power RK3576_PD_SDGMAC>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@2a310000 { compatible = "rockchip,rk3576-dw-mshc"; reg = <0x0 0x2a310000 0x0 0x4000>; @@ -1260,6 +1718,179 @@ status = "disabled"; }; + sfc0: spi@2a340000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a340000 0x0 0x4000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + power-domains = <&power RK3576_PD_NVM>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rng: rng@2a410000 { + compatible = "rockchip,rk3576-rng"; + reg = <0x0 0x2a410000 0x0 0x200>; + clocks = <&cru HCLK_TRNG_NS>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cru SRST_H_TRNG_NS>; + }; + + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names = "otp", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpub_leakage: cpub-leakage@1e { + reg = <0x1e 0x1>; + }; + cpul_leakage: cpul-leakage@1f { + reg = <0x1f 0x1>; + }; + npu_leakage: npu-leakage@20 { + reg = <0x20 0x1>; + }; + gpu_leakage: gpu-leakage@21 { + reg = <0x21 0x1>; + }; + log_leakage: log-leakage@22 { + reg = <0x22 0x1>; + }; + }; + + sai0: sai@2a600000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a600000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai0m0_lrck + &sai0m0_sclk + &sai0m0_sdi0 + &sai0m0_sdi1 + &sai0m0_sdi2 + &sai0m0_sdi3 + &sai0m0_sdo0 + &sai0m0_sdo1 + &sai0m0_sdo2 + &sai0m0_sdo3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI0"; + status = "disabled"; + }; + + sai1: sai@2a610000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a610000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0 + &sai1m0_sdo1 + &sai1m0_sdo2 + &sai1m0_sdo3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI1"; + status = "disabled"; + }; + + sai2: sai@2a620000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a620000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_lrck + &sai2m0_sclk + &sai2m0_sdi + &sai2m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI2"; + status = "disabled"; + }; + + sai3: sai@2a630000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a630000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai3m0_lrck + &sai3m0_sclk + &sai3m0_sdi + &sai3m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI3"; + status = "disabled"; + }; + + sai4: sai@2a640000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a640000 0x0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 0>, <&dmac2 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai4m0_lrck + &sai4m0_sclk + &sai4m0_sdi + &sai4m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI4"; + status = "disabled"; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, @@ -1371,7 +2002,6 @@ status = "disabled"; }; - i2c6: i2c@2ac90000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ac90000 0x0 0x1000>; @@ -1756,6 +2386,19 @@ status = "disabled"; }; + hdptxphy: hdmiphy@2b000000 { + compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0x2b000000 0x0 0x2000>; + clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; + clock-names = "ref", "apb"; + resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, + <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + sram: sram@3ff88000 { compatible = "mmio-sram"; reg = <0x0 0x3ff88000 0x0 0x78000>; @@ -1773,74 +2416,6 @@ compatible = "arm,scmi-shmem"; reg = <0x0 0x4010f000 0x0 0x100>; }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3576-pinctrl"; - rockchip,grf = <&ioc_grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@27320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x27320000 0x0 0x200>; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2ae10000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae10000 0x0 0x200>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2ae20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae20000 0x0 0x200>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2ae30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae30000 0x0 0x200>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@2ae40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae40000 0x0 0x200>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi index a3138d2d384c..e44125e9a8fb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi @@ -114,6 +114,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 08f09053a066..ae9274365bed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3588.dtsi" / { @@ -33,6 +34,17 @@ "Headphone", "Headphones"; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -164,6 +176,30 @@ status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -258,6 +294,10 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + /* phy1 - right ethernet port */ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -268,6 +308,22 @@ &pcie2x1l1 { reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x310000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; }; /* phy0 - left ethernet port */ @@ -286,6 +342,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -723,3 +783,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts index 779cd1b1798c..6ad2759ddcca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3588-armsom-lm7.dtsi" / { @@ -32,6 +33,28 @@ pinctrl-0 = <&hp_detect>; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -138,6 +161,54 @@ status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -192,6 +263,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &package_thermal { polling-delay = <1000>; @@ -406,3 +485,25 @@ &usb_host2_xhci { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index c3abdfb04f8f..70f03e68ba55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/rockchip,rk3588-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> #include <dt-bindings/phy/phy.h> @@ -95,8 +96,6 @@ enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -173,8 +172,6 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -213,8 +210,6 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -358,11 +353,6 @@ }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - scmi: scmi { compatible = "arm,scmi-smc"; arm,smc-id = <0x82000010>; @@ -382,6 +372,22 @@ }; }; + hdmi0_sound: hdmi0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi0"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; @@ -428,16 +434,15 @@ #clock-cells = <0>; }; - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - scmi_shmem: sram@0 { + scmi_shmem: shmem@10f000 { compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; }; }; @@ -579,6 +584,16 @@ reg = <0x0 0xfd58c000 0x0 0x1000>; }; + mipidcphy0_grf: syscon@fd5e8000 { + compatible = "rockchip,rk3588-dcphy-grf", "syscon"; + reg = <0x0 0xfd5e8000 0x0 0x4000>; + }; + + mipidcphy1_grf: syscon@fd5ec000 { + compatible = "rockchip,rk3588-dcphy-grf", "syscon"; + reg = <0x0 0xfd5ec000 0x0 0x4000>; + }; + vop_grf: syscon@fd5a4000 { compatible = "rockchip,rk3588-vop-grf", "syscon"; reg = <0x0 0xfd5a4000 0x0 0x2000>; @@ -864,7 +879,7 @@ }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg = <RK3588_PD_GPU>; clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, @@ -1261,14 +1276,16 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; @@ -1318,6 +1335,21 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; + dma-names = "tx"; + dmas = <&dmac1 6>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1335,6 +1367,21 @@ status = "disabled"; }; + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF3_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + dma-names = "tx"; + dmas = <&dmac1 7>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s5_8ch: i2s@fddf0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf0000 0x0 0x1000>; @@ -1369,6 +1416,62 @@ status = "disabled"; }; + dsi0: dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys"; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy0 PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + }; + + dsi0_out: port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi@fde30000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde30000 0x0 0x10000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; + clock-names = "pclk", "sys"; + resets = <&cru SRST_P_DSIHOST1>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy1 PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + }; + + dsi1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfde80000 0x0 0x20000>; @@ -1385,7 +1488,7 @@ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "avp", "cec", "earc", "main", "hpd"; - phys = <&hdptxphy_hdmi0>; + phys = <&hdptxphy0>; pinctrl-names = "default"; pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; @@ -1394,6 +1497,7 @@ reset-names = "ref", "hdp"; rockchip,grf = <&sys_grf>; rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -1410,6 +1514,34 @@ }; }; + edp0: edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfdec0000 0x0 0x1000>; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; + clock-names = "dp", "pclk"; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&hdptxphy0>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp0_in: port@0 { + reg = <0>; + }; + + edp0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; @@ -1921,6 +2053,14 @@ status = "disabled"; }; + rng@fe378000 { + compatible = "rockchip,rk3588-rng"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; + }; + i2s0_8ch: i2s@fe470000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfe470000 0x0 0x1000>; @@ -2016,12 +2156,47 @@ status = "disabled"; }; + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + dma-names = "tx"; + dmas = <&dmac0 5>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif0m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + dma-names = "tx"; + dmas = <&dmac1 5>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif1m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ <0x0 0xfe680000 0 0x100000>; /* GICR */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; + dma-noncoherent; mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; @@ -2033,6 +2208,7 @@ its0: msi-controller@fe640000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe640000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2040,6 +2216,7 @@ its1: msi-controller@fe660000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe660000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2807,11 +2984,12 @@ #dma-cells = <1>; }; - hdptxphy_hdmi0: phy@fed60000 { + hdptxphy0: phy@fed60000 { compatible = "rockchip,rk3588-hdptx-phy"; reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, @@ -2845,6 +3023,38 @@ status = "disabled"; }; + mipidcphy0: phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy0_grf>; + clocks = <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <1>; + status = "disabled"; + }; + + mipidcphy1: phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfedb0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy1_grf>; + clocks = <&cru PCLK_MIPI_DCPHY1>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1_GRF>, + <&cru SRST_S_MIPI_DCPHY1>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <1>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts index 9d525c8ff725..3d5c8b753208 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -23,17 +23,28 @@ pwms = <&pwm2 0 25000 0>; }; - hdmi-con { + hdmi0-con { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con_in: endpoint { + hdmi0_con_in: endpoint { remote-endpoint = <&hdmi0_out_con>; }; }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -117,6 +128,10 @@ status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -125,11 +140,45 @@ &hdmi0_out { hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; }; }; -&hdptxphy_hdmi0 { +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { status = "okay"; }; @@ -261,3 +310,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts index bc6b43a77153..738637ecaf55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -148,6 +148,40 @@ }; }; +&edp1 { + force-hpd; + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + hpd-absent-delay-ms = <200>; + no-hpd; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp1_in { + edp1_in_vp2: endpoint { + remote-endpoint = <&vp2_out_edp1>; + }; +}; + +&edp1_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; + + /* HDMI CEC is not used */ &hdmi0 { pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; @@ -166,7 +200,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -383,6 +421,8 @@ }; &vop { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; status = "okay"; }; @@ -396,3 +436,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp2 { + vp2_out_edp1: endpoint@ROCKCHIP_VOP2_EP_EDP1 { + reg = <ROCKCHIP_VOP2_EP_EDP1>; + remote-endpoint = <&edp1_in_vp2>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index 71ed680621b8..cc37f082adea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 5e72d0eff0e0..8a783dc64c0e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -126,6 +126,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_user_en: led_user_en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 7125790bbed2..08920344a4b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -4,12 +4,24 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/soc/rockchip,vop2.h> / { chosen { stdout-path = "serial2:1500000n8"; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -81,6 +93,26 @@ status = "okay"; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -275,3 +307,18 @@ &usb_host2_xhci { status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index ba49f0bbaac6..8e912da299a2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -132,6 +132,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { compatible = "regulator-fixed"; regulator-name = "pcie20_avdd0v85"; @@ -364,7 +375,27 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -441,7 +472,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -519,6 +550,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { @@ -1371,11 +1406,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -1385,3 +1420,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts new file mode 100644 index 000000000000..91fe810d38d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip RK3588 EVB2 V10 Board"; + compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: regulator-vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + non-removable; + no-sd; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-0 = <&wifi_host_wake_irq>; + pinctrl-names = "default"; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + /* regulator coupling requires always-on */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-coupled-with = <&vdd_gpu_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + /* regulator coupling requires always-on */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-coupled-with = <&vdd_gpu_s0>; + regulator-coupled-max-spread = <10000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 840b638af1c2..90414486e466 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -7,6 +7,46 @@ #include "rk3588-extra-pinctrl.dtsi" / { + hdmi1_sound: hdmi1-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi1"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi1>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s6_8ch>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The 4k HDMI capture controller works only with 32bit + * phys addresses and doesn't support IOMMU. HDMI RX CMA + * must be reserved below 4GB. + * The size of 160MB was determined as follows: + * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB + * To ensure sufficient support for practical use-cases, + * we doubled the 66MB value. + */ + hdmi_receiver_cma: hdmi-receiver-cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x0 0x0 0xffffffff>; + size = <0x0 (160 * 0x100000)>; /* 160MiB */ + alignment = <0x0 0x40000>; /* 64K */ + no-map; + status = "disabled"; + }; + }; + usb_host1_xhci: usb@fc400000 { compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; @@ -67,6 +107,26 @@ }; }; + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; + dma-names = "tx"; + dmas = <&dmac1 22>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -84,6 +144,21 @@ status = "disabled"; }; + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF4_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + dma-names = "tx"; + dmas = <&dmac1 8>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s6_8ch: i2s@fddf4000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf4000 0x0 0x1000>; @@ -135,6 +210,107 @@ status = "disabled"; }; + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfdea0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX1>, + <&cru CLK_HDMITX1_EARC>, + <&cru CLK_HDMITX1_REF>, + <&cru MCLK_I2S6_8CH_TX>, + <&cru CLK_HDMIHDP1>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + }; + + hdmi1_out: port@1 { + reg = <1>; + }; + }; + }; + + edp1: edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfded0000 0x0 0x1000>; + clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>; + clock-names = "dp", "pclk"; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&hdptxphy1>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp1_in: port@0 { + reg = <0>; + }; + + edp1_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_receiver: hdmi_receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + memory-region = <&hdmi_receiver_cma>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + rockchip,grf = <&sys_grf>; + rockchip,vo1-grf = <&vo1_grf>; + status = "disabled"; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -398,6 +574,23 @@ }; }; + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + status = "disabled"; + }; + usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>; @@ -449,3 +642,24 @@ status = "disabled"; }; }; + +&vop { + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>, + <&hdptxphy1>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "pll_hdmiphy0", + "pll_hdmiphy1"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi index 390051317389..4331cdc70f97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -205,6 +205,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_rgb_b: led-rgb-b { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi index 42c523b553c9..80e16ea4154c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi @@ -108,6 +108,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi new file mode 100644 index 000000000000..6726eeb49255 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3588.dtsi" + +/ { + compatible = "firefly,icore-3588q", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts index 2be5251d3e3b..e086114c7634 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts @@ -337,7 +337,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index b3a04ca370bb..8171fbfd819a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -335,7 +335,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99fc..af431fdcbea7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -222,6 +222,10 @@ compatible = "realtek,rt5616"; reg = <0x1b>; #sound-dai-cells = <0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; }; }; @@ -256,6 +260,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts index 4791b77f3571..73d8ce4fde2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts @@ -140,6 +140,24 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx0>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; }; &combphy0_ps { @@ -207,7 +225,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -316,6 +334,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -400,6 +422,12 @@ status = "okay"; }; +&spdif_tx0 { + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m1_tx>; + status = "okay"; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso new file mode 100644 index 000000000000..9d44dfe2f30d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 Cherry Embedded Solutions GmbH + * + * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine + * connector on RK3588 Jaguar. + * + * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary + * camera connectors (each their own I2C bus, clock, reset and PWM lines as well + * as 2-lane CSI). + * + * This adapter routes some GPIOs to power rails and loops together some other + * GPIOs. + * + * This adapter is used during manufacturing for validating proper soldering of + * the mezzanine connector. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3_s3>; + }; + + pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gpio3 { + pinctrl-0 = <&pre_ict_pwr2gpio>; + pinctrl-names = "default"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2x1l2_perstn_m0>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */ + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pinctrl { + pcie2x1l2 { + pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pre-ict-tester { + pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins { + rockchip,pins = + /* + * GPIO3_A3 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_2 is properly routed, GPIO3_A3 should be + * LOW. The signal shall not read HIGH in the event + * GPIO3_A3 isn't properly routed due to soldering + * issue. Therefore, let's enforce a pull-up (which is + * the SoC default for this pin). + */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power + * rail. It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_B2 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_1 is properly routed, GPIO3_B2 should be + * LOW. This is an issue if GPIO3_B2 isn't properly + * routed due to soldering issue, because GPIO3_B2 + * default bias is pull-down therefore being LOW. So + * the worst case scenario and the pass scenario expect + * the same value. Make GPIO3_B2 a pull-up so that a + * soldering issue on GPIO3_B2 reports HIGH but proper + * soldering reports LOW. + */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power + * rail. It should be HIGH if all is properly soldered. + * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't + * properly routed due to soldering issue, because + * GPIO3_C6 default bias is pull-up therefore being HIGH + * in all cases: + * - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not + * routed properly, + * - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is + * not routed properly, + * - GPIO3_C6 is HIGH if everything is proper, + * Make GPIO3_C6 a pull-down so that a soldering issue + * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper + * soldering reports HIGH. + */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D2 is routed to VCC_5V0_1 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D3 is routed to VCC_5V0_2 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 90f823b2c219..ebe77cdd24e8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -303,7 +303,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -333,6 +337,56 @@ }; }; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int1>; + vbus-supply = <&vcc_5v0_usb_c1>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-1 P11"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + vdd_npu_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -394,6 +448,56 @@ pinctrl-0 = <&i2c8m2_xfer>; status = "okay"; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int2>; + vbus-supply = <&vcc_5v0_usb_c2>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-2 P12"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc1_hs: endpoint { + remote-endpoint = <&usb_host1_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc1_ss: endpoint { + remote-endpoint = <&usbdp_phy1_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc1_sbu: endpoint { + remote-endpoint = <&usbdp_phy1_typec_sbu>; + }; + }; + }; + }; + }; + vdd_cpu_big0_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -412,6 +516,10 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio0 { rgmii_phy: ethernet-phy@6 { /* KSZ9031 or KSZ9131 */ @@ -451,6 +559,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -483,6 +595,26 @@ rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; }; }; + + usb3 { + cc_int1: cc-int1 { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cc_int2: cc-int2 { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + typec0_sbu_dc_pins: typec0-sbu-dc-pins { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + typec1_sbu_dc_pins: typec1-sbu-dc-pins { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &saradc { @@ -503,7 +635,6 @@ non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; - supports-cqe; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vcc_1v8_s3>; status = "okay"; @@ -851,6 +982,24 @@ status = "okay"; }; +/* USB-C P11 connector */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +/* USB-C P12 connector */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -893,6 +1042,56 @@ status = "okay"; }; +/* Type-C on P11 */ +&usbdp_phy0 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec0_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +/* Type-C on P12 */ +&usbdp_phy1 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec1_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy1_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_ss>; + }; + + usbdp_phy1_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc1_sbu>; + }; + }; +}; + /* host0 on P10 USB-A */ &usb_host0_ehci { status = "okay"; @@ -903,6 +1102,36 @@ status = "okay"; }; +/* host0 on P11 USB-C */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +/* host1 on P12 USB-C */ +&usb_host1_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host1_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc1_hs>; + }; + }; +}; + /* host1 on M.2 E-key */ &usb_host1_ehci { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts new file mode 100644 index 000000000000..78a4e896f665 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 MNT Research GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> + +#include "rk3588-firefly-icore-3588q.dtsi" + +/ { + model = "MNT Reform 2 with RCORE RK3588 Module"; + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; + chassis-type = "laptop"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 8 16 32 64 128 160 200 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm8 0 10000 0>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie30_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout + ð_phy_reset>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_hdmi0>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1l2 { + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_reset: eth-phy-reset { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <40000000>; + no-1-8-v; + no-mmc; + no-sdio; + vmmc-supply = <&vcc3v3_pcie30>; + vqmmc-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp2>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index cb350727d116..3d8b6f0c5541 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -52,6 +52,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; @@ -163,8 +174,6 @@ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&typec5v_pwren>; - regulator-always-on; - regulator-boot-on; regulator-name = "vbus5v0_typec"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -177,8 +186,6 @@ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb5v_pwren>; - regulator-always-on; - regulator-boot-on; regulator-name = "vbus5v0_usb"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -360,7 +367,35 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -426,24 +461,30 @@ }; &i2c6 { - clock-frequency = <200000>; status = "okay"; - fusb302: typec-portc@22 { + usbc0: usb-typec@22 { compatible = "fcs,fusb302"; reg = <0x22>; interrupt-parent = <&gpio0>; interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&usbc0_int>; pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; vbus-supply = <&vbus5v0_typec>; + status = "okay"; connector { compatible = "usb-c-connector"; data-role = "dual"; label = "USB-C"; - power-role = "source"; + op-sink-microwatt = <1000000>; + /* fusb302 supports PD Rev 2.0 Ver 1.2 */ + pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; + power-role = "dual"; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + try-power-role = "source"; + typec-power-opmode = "1.5A"; ports { #address-cells = <1>; @@ -531,6 +572,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &pcie2x1l0 { reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc_3v3_pcie20>; @@ -565,6 +614,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { @@ -1084,9 +1137,8 @@ }; &usb_host0_xhci { - dr_mode = "host"; - status = "okay"; usb-role-switch; + status = "okay"; port { usb_host0_xhci_drd_sw: endpoint { @@ -1122,3 +1174,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index 1c0851b45eb8..fbe1d5c06d90 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi index 87090cb98020..9343dfc86941 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi @@ -7,9 +7,6 @@ #include "rk3588-orangepi-5.dtsi" / { - model = "Xunlong Orange Pi 5 Max"; - compatible = "xunlong,orangepi-5-max", "rockchip,rk3588"; - vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -62,18 +59,12 @@ &led_blue_pwm { /* PWM_LED1 */ - pwms = <&pwm4 0 25000 0>; status = "okay"; }; -&led_green_pwm { - /* PWM_LED2 */ - pwms = <&pwm5 0 25000 0>; -}; - /* phy2 */ &pcie2x1l1 { - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie_eth>; status = "okay"; }; @@ -96,6 +87,20 @@ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wireless-bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm4 { @@ -129,6 +134,28 @@ phy-supply = <&vcc5v0_usb20>; }; +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer &uart7m0_ctsn &uart7m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on>, <&host_wake_bt>, <&bt_wake_host>; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts index ce44549babf4..8b1d35760c3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts @@ -21,6 +21,17 @@ }; }; }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; }; &hdmi0 { @@ -39,10 +50,57 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { status = "okay"; }; +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 0>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 0>; +}; + &pinctrl { usb { @@ -58,3 +116,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 255e33c5dbdc..121e4d1c3fa5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -26,6 +26,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; @@ -113,6 +124,10 @@ status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -125,7 +140,31 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -189,6 +228,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &led_blue_gpio { gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -342,3 +389,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts new file mode 100644 index 000000000000..f8c6c080e418 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3588-orangepi-5-compact.dtsi" + +/ { + model = "Xunlong Orange Pi 5 Ultra"; + compatible = "xunlong,orangepi-5-ultra", "rockchip,rk3588"; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; +}; + +&pinctrl { + usb { + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc5v0_usb30_otg { + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi index a98e804a0949..91d56c34a1e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi @@ -276,7 +276,7 @@ /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -348,6 +348,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index 088cfade6f6f..78aaa6635b5d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -311,7 +311,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; @@ -347,6 +347,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 6d68f70284e4..7de17117df7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -11,6 +11,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "dt-bindings/usb/pd.h" #include "rk3588.dtsi" @@ -72,6 +73,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -261,6 +273,28 @@ status = "okay"; }; +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -564,6 +598,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { @@ -690,10 +728,9 @@ &sdhci { bus-width = <8>; - max-frequency = <200000000>; + max-frequency = <150000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; - mmc-hs200-1_8v; no-sdio; no-sd; non-removable; @@ -1209,3 +1246,18 @@ rockchip,dp-lane-mux = <2 3>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts new file mode 100644 index 000000000000..74c7b6502e4d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588-rock-5b.dtsi" + +/ { + model = "Radxa ROCK 5B+"; + compatible = "radxa,rock-5b-plus", "rockchip,rk3588"; + + rfkill-wwan { + compatible = "rfkill-gpio"; + label = "rfkill-m2-wwan"; + radio-type = "wwan"; + shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_4g: regulator-vcc3v3-4g { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */ + regulator-name = "vcc3v3_4g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_wwan_pwr: regulator-vcc3v3-wwan { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wwan_power_en>; + regulator-name = "vcc3v3_wwan_pwr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_4g>; + }; +}; + +&gpio0 { + wwan-disable2-n-hog { + gpios = <RK_PB2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M.2 B-key W_DISABLE2#"; + gpio-hog; + }; +}; + +&gpio2 { + wwan-reset-n-hog { + gpios = <RK_PB3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M.2 B-key RESET#"; + gpio-hog; + }; + + wwan-wake-n-hog { + gpios = <RK_PB2 GPIO_ACTIVE_LOW>; + input; + line-name = "M.2 B-key WoWWAN#"; + gpio-hog; + }; +}; + +&pcie30phy { + data-lanes = <1 1 2 2>; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <2>; +}; + +&pinctrl { + wwan { + wwan_power_en: wwan-pwr-en { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc5v0_host { + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index d597112f1d5b..9407a7c9910a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -2,462 +2,11 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/soc/rockchip,vop2.h> -#include "rk3588.dtsi" +#include "rk3588-rock-5b.dtsi" / { model = "Radxa ROCK 5B"; compatible = "radxa,rock-5b", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - analog-sound { - compatible = "audio-graph-card"; - label = "rk3588-es8316"; - - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - - dais = <&i2s0_8ch_p0>; - hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - }; - - hdmi0-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con_in: endpoint { - remote-endpoint = <&hdmi0_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_rgb_b>; - - led_rgb_b { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_BLUE>; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; - }; - - rfkill { - compatible = "rfkill-gpio"; - label = "rfkill-m2-wlan"; - radio-type = "wlan"; - shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - - rfkill-bt { - compatible = "rfkill-gpio"; - label = "rfkill-m2-bt"; - radio-type = "bluetooth"; - shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - - vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_vcc3v3_en>; - regulator-name = "vcc3v3_pcie2x1l0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie30: regulator-vcc3v3-pcie30 { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; -}; - -&hdmi0_in { - hdmi0_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi0>; - }; -}; - -&hdmi0_out { - hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi0_con_in>; - }; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&package_thermal { - polling-delay = <1000>; - - trips { - package_fan0: package-fan0 { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - package_fan1: package-fan1 { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map0 { - trip = <&package_fan0>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map1 { - trip = <&package_fan1>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&pcie2x1l0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; - status = "okay"; -}; - -&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_rgb_b: led-rgb-b { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_0_vcc3v3_en: pcie2-0-vcc-en { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; }; &sdio { @@ -481,427 +30,23 @@ status = "okay"; }; -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim2_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - &uart6 { pinctrl-names = "default"; pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; status = "okay"; }; -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - /* connected to USB hub, which is powered by vcc5v0_sys */ - phy-supply = <&vcc5v0_sys>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = <ROCKCHIP_VOP2_EP_HDMI0>; - remote-endpoint = <&hdmi0_in_vp0>; - }; +&vcc5v0_host { + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi new file mode 100644 index 000000000000..6052787d2560 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi @@ -0,0 +1,945 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3588.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + led_rgb_b { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 120 150 180 210 240 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-m2-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + rfkill-bt { + compatible = "rfkill-gpio"; + label = "rfkill-m2-bt"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_vcc3v3_en>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_vcc3v3_en: pcie2-0-vcc-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso new file mode 100644 index 000000000000..b8636fcb4f39 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Tiger system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8-video"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-name = "vcc2v8-video"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_panel_in: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp3: endpoint { + remote-endpoint = <&vp3_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_panel: endpoint { + remote-endpoint = <&mipi_panel_in>; + }; +}; + +&i2c6 { + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int>; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pca9670_resetn>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + }; +}; + +&mipidcphy0 { + status = "okay"; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&vp3 { + #address-cells = <1>; + #size-cells = <0>; + + vp3_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = <ROCKCHIP_VOP2_EP_MIPI0>; + remote-endpoint = <&dsi0_in_vp3>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 3187b4918a30..caa43d1abf17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -189,7 +189,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -228,6 +232,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &pcie30phy { status = "okay"; }; @@ -310,8 +318,10 @@ status = "okay"; }; +/* DB9 RS232/RS485 when SW2 in "UART1" mode */ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; }; &usbdp_phy0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 81a6a05ce13b..c4933a08dd1e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -173,7 +173,6 @@ &i2c2 { pinctrl-0 = <&i2c2m3_xfer>; - status = "okay"; }; &i2c2m3_xfer { @@ -336,6 +335,10 @@ reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -386,7 +389,6 @@ non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; - supports-cqe; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vcc_1v8_s3>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 3cbee5b97470..5a428e00ab93 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -289,6 +289,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { rtl8211f { rtl8211f_rst: rtl8211f-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6bc46734cc14..60ad272982ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -214,6 +214,8 @@ }; &package_thermal { + polling-delay = <1000>; + trips { package_active1: trip-active1 { temperature = <45000>; @@ -287,6 +289,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index bce72bac4503..3045cb3bd68c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -11,20 +11,15 @@ compatible = "operating-points-v2"; opp-shared; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <750000 750000 950000>; clock-latency-ns = <40000>; opp-suspend; }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <887500 887500 950000>; - clock-latency-ns = <40000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <937500 937500 950000>; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <775000 775000 950000>; clock-latency-ns = <40000>; }; }; @@ -33,9 +28,14 @@ compatible = "operating-points-v2"; opp-shared; + opp-1200000000{ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <750000 750000 950000>; + opp-microvolt = <762500 762500 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { @@ -43,25 +43,20 @@ opp-microvolt = <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <875000 875000 950000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; cluster2_opp_table: opp-table-cluster2 { compatible = "operating-points-v2"; opp-shared; + opp-1200000000{ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <750000 750000 950000>; + opp-microvolt = <762500 762500 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { @@ -69,16 +64,6 @@ opp-microvolt = <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <875000 875000 950000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; gpu_opp_table: opp-table { @@ -104,10 +89,6 @@ opp-hz = /bits/ 64 <700000000>; opp-microvolt = <750000 750000 850000>; }; - opp-850000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <787500 787500 850000>; - }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 9c394f733bbf..8b717c4017a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -236,7 +236,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -361,6 +361,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -429,7 +433,7 @@ }; &pwm13 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm13m2_pins>; status = "okay"; }; @@ -803,6 +807,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -832,6 +844,16 @@ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; }; +&usbdp_phy0 { + /* + * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally + * the differential pairs 0+1 and the aux channel are wired to a + * mini DP connector. + */ + rockchip,dp-lane-mux = <0 1>; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; @@ -840,6 +862,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&u2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts index bc4077575beb..0df3e80f2dd9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include <dt-bindings/usb/pd.h> #include "rk3588s.dtsi" @@ -238,11 +239,47 @@ status = "okay"; }; +&edp0 { + force-hpd; + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + no-hpd; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp0_in { + edp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_edp0>; + }; +}; + +&edp0_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c3 { status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -340,6 +377,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { @@ -399,6 +440,7 @@ }; &pwm12 { + pinctrl-0 = <&pwm12m1_pins>; status = "okay"; }; @@ -1168,3 +1210,20 @@ }; }; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; + status = "okay"; +}; + +&vp2 { + vp2_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 { + reg = <ROCKCHIP_VOP2_EP_EDP0>; + remote-endpoint = <&edp0_in_vp2>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 812bba0aef1a..873a2bd6a6de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -611,7 +611,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -675,6 +675,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio-amplifier { headphone_amplifier_en: headphone-amplifier-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index 4a3aa80f2226..4ec7bc4a9e96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -278,7 +278,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -412,7 +416,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -449,12 +453,20 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + &pcie2x1l2 { pinctrl-0 = <&rtl8111_perstb>; pinctrl-names = "default"; status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { bluetooth-pins { bt_reset: bt-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index ac48e7fd3923..2c22abaf40a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -6,6 +6,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3588s.dtsi" / { @@ -42,6 +43,17 @@ pinctrl-0 = <&ir_receiver_pin>; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + leds { compatible = "pwm-leds"; @@ -181,6 +193,34 @@ status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -233,6 +273,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { @@ -693,8 +741,24 @@ &uart9 { pinctrl-names = "default"; - pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_host_irq &bt_wake_pin &bt_reset_pin>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; }; &u2phy2 { @@ -734,3 +798,18 @@ &usb_host2_xhci { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index d2eddea1840f..fbf062ec3bf1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -251,7 +251,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts index 8f034c6d494c..a72063c55140 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts @@ -264,7 +264,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -433,6 +433,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { lcd { lcd_pwren: lcd-pwren { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index d86aeacca238..4fedc50cce8c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -197,7 +197,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -268,7 +272,7 @@ status = "okay"; es8388: audio-codec@10 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x10>; clocks = <&cru I2S1_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -355,6 +359,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -365,6 +373,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 70a43432bdc5..f894742b1ebe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -334,7 +334,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { io_led: io-led { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index 9b14d5383cdc..dd7317bab613 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -68,10 +68,10 @@ }; }; - fan { + fan: fan { compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-levels = <0 64 128 192 255>; + cooling-levels = <0 24 44 64 128 192 255>; fan-supply = <&vcc_5v0>; pwms = <&pwm3 0 10000 0>; }; @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -417,6 +417,36 @@ }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l2 { pinctrl-names = "default"; pinctrl-0 = <&pcie20x1_2_perstn_m0>; @@ -425,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_pins: led-pins { @@ -843,6 +877,8 @@ }; &tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ status = "okay"; }; |